scholarly journals A low-latency real-time PAM-4 receiver enabled by deep-parallel technique

2021 ◽  
pp. 127836
Author(s):  
Liuyan Chen ◽  
Chao Li ◽  
Chin Wan Oh ◽  
A.M.J. Koonen
Sensors ◽  
2021 ◽  
Vol 21 (11) ◽  
pp. 3715
Author(s):  
Ioan Ungurean ◽  
Nicoleta Cristina Gaitan

In the design and development process of fog computing solutions for the Industrial Internet of Things (IIoT), we need to take into consideration the characteristics of the industrial environment that must be met. These include low latency, predictability, response time, and operating with hard real-time compiling. A starting point may be the reference fog architecture released by the OpenFog Consortium (now part of the Industrial Internet Consortium), but it has a high abstraction level and does not define how to integrate the fieldbuses and devices into the fog system. Therefore, the biggest challenges in the design and implementation of fog solutions for IIoT is the diversity of fieldbuses and devices used in the industrial field and ensuring compliance with all constraints in terms of real-time compiling, low latency, and predictability. Thus, this paper proposes a solution for a fog node that addresses these issues and integrates industrial fieldbuses. For practical implementation, there are specialized systems on chips (SoCs) that provides support for real-time communication with the fieldbuses through specialized coprocessors and peripherals. In this paper, we describe the implementation of the fog node on a system based on Xilinx Zynq UltraScale+ MPSoC ZU3EG A484 SoC.


Author(s):  
Olivier Jaubert ◽  
Javier Montalt‐Tordera ◽  
Dan Knight ◽  
Gerry J. Coghlan ◽  
Simon Arridge ◽  
...  

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 689
Author(s):  
Tom Springer ◽  
Elia Eiroa-Lledo ◽  
Elizabeth Stevens ◽  
Erik Linstead

As machine learning becomes ubiquitous, the need to deploy models on real-time, embedded systems will become increasingly critical. This is especially true for deep learning solutions, whose large models pose interesting challenges for target architectures at the “edge” that are resource-constrained. The realization of machine learning, and deep learning, is being driven by the availability of specialized hardware, such as system-on-chip solutions, which provide some alleviation of constraints. Equally important, however, are the operating systems that run on this hardware, and specifically the ability to leverage commercial real-time operating systems which, unlike general purpose operating systems such as Linux, can provide the low-latency, deterministic execution required for embedded, and potentially safety-critical, applications at the edge. Despite this, studies considering the integration of real-time operating systems, specialized hardware, and machine learning/deep learning algorithms remain limited. In particular, better mechanisms for real-time scheduling in the context of machine learning applications will prove to be critical as these technologies move to the edge. In order to address some of these challenges, we present a resource management framework designed to provide a dynamic on-device approach to the allocation and scheduling of limited resources in a real-time processing environment. These types of mechanisms are necessary to support the deterministic behavior required by the control components contained in the edge nodes. To validate the effectiveness of our approach, we applied rigorous schedulability analysis to a large set of randomly generated simulated task sets and then verified the most time critical applications, such as the control tasks which maintained low-latency deterministic behavior even during off-nominal conditions. The practicality of our scheduling framework was demonstrated by integrating it into a commercial real-time operating system (VxWorks) then running a typical deep learning image processing application to perform simple object detection. The results indicate that our proposed resource management framework can be leveraged to facilitate integration of machine learning algorithms with real-time operating systems and embedded platforms, including widely-used, industry-standard real-time operating systems.


Author(s):  
Patrick Dietrich ◽  
Christoph Munkelt ◽  
Kevin Srokos ◽  
Martin Landmann ◽  
Stefan Heist ◽  
...  

2010 ◽  
Vol 12 (S1) ◽  
Author(s):  
Haris Saybasili ◽  
J Andrew Derbyshire ◽  
Peter Kellman ◽  
Mark A Griswold ◽  
Cengizhan Ozturk ◽  
...  

Author(s):  
David R. Selviah ◽  
Janti Shawash

This chapter celebrates 50 years of first and higher order neural network (HONN) implementations in terms of the physical layout and structure of electronic hardware, which offers high speed, low latency, compact, low cost, low power, mass produced systems. Low latency is essential for practical applications in real time control for which software implementations running on CPUs are too slow. The literature review chapter traces the chronological development of electronic neural networks (ENN) discussing selected papers in detail from analog electronic hardware, through probabilistic RAM, generalizing RAM, custom silicon Very Large Scale Integrated (VLSI) circuit, Neuromorphic chips, pulse stream interconnected neurons to Application Specific Integrated circuits (ASICs) and Zero Instruction Set Chips (ZISCs). Reconfigurable Field Programmable Gate Arrays (FPGAs) are given particular attention as the most recent generation incorporate Digital Signal Processing (DSP) units to provide full System on Chip (SoC) capability offering the possibility of real-time, on-line and on-chip learning.


Technologies ◽  
2019 ◽  
Vol 7 (1) ◽  
pp. 22
Author(s):  
Ramiro Sámano-Robles

This paper investigates backlog retransmission strategies for a class of random access protocols with retransmission diversity (i.e., network diversity multiple access or NDMA) combined with multiple-antenna-based multi-packet reception (MPR). This paper proposes NDMA-MPR as a candidate for 5G contention-based and ultra-low latency multiple access. This proposal is based on the following known features of NDMA-MPR: (1) near collision-free performance, (2) very low latency values, and (3) reduced feedback complexity (binary feedback). These features match the machine-type traffic, real-time, and dense object connectivity requirements in 5G. This work is an extension of previous works using a multiple antenna receiver with correlated Rice channels and co-channel interference modelled as a Rayleigh fading variable. Two backlog retransmission strategies are implemented: persistent and randomized. Boundaries and extended analysis of the system are here obtained for different network and channel conditions. Average delay is evaluated using the M/G/1 queue model with statistically independent vacations. The results suggest that NDMA-MPR can achieve very low values of latency that can guarantee real- or near-real-time performance for multiple access in 5G, even in scenarios with high correlation and moderate co-channel interference.


Sign in / Sign up

Export Citation Format

Share Document