Designing layout–timing independent quantum-dot cellular automata (QCA) circuits by global asynchrony

Multiplexers are extremely important parts of signal control systems. Some critical circuits of computing systems, like memories, use large multiplexers in order to present the value of a specific memory cell to their output. Several quantum-dot cellular automata (QCA) circuits have been designed and the need for a QCA memory access system becomes prominent. A modular 2n to 1 QCA multiplexer covering small area could reduce the size of such circuits and conclusively could increase circuit integration. In this paper we present a novel design of a small size, modular quantum-dot cellular automata (QCA) 2n to 1 multiplexer that can be used for memory addressing. The design objective is to develop a modular design methodology which can be used to implement 2n to 1 multiplexers using building blocks. For the QCA implementation a careful consideration is taken into account concerning the design in order to increase the circuit stability.

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Accurate reliability analysis method for quantum-dot cellular automata circuits

International Journal of Modern Physics B ◽

10.1142/s0217979215502033 ◽

2015 ◽

Vol 29 (29) ◽

pp. 1550203

Author(s):

Huanqing Cui ◽

Li Cai ◽

Sen Wang ◽

Xiaoqiang Liu ◽

Xiaokuo Yang

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Fault Tree ◽

The Novel ◽

Binary Decision ◽

Quantum Dot Cellular Automata ◽

Input Signals ◽

Tree Models ◽

The Impact ◽

Qca Circuits

Probabilistic transfer matrix (PTM) is a widely used model in the reliability research of circuits. However, PTM model cannot reflect the impact of input signals on reliability, so it does not completely conform to the mechanism of the novel field-coupled nanoelectronic device which is called quantum-dot cellular automata (QCA). It is difficult to get accurate results when PTM model is used to analyze the reliability of QCA circuits. To solve this problem, we present the fault tree models of QCA fundamental devices according to different input signals. After that, the binary decision diagram (BDD) is used to quantitatively investigate the reliability of two QCA XOR gates depending on the presented models. By employing the fault tree models, the impact of input signals on reliability can be identified clearly and the crucial components of a circuit can be found out precisely based on the importance values (IVs) of components. So this method is contributive to the construction of reliable QCA circuits.

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Implementing Logical Circuits with Four Phase Quantum Dot Cellular Clock using QCA Designer

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.e6423.018520 ◽

2020 ◽

Vol 8 (5) ◽

pp. 3999-4003

Keyword(s):

Energy Consumption ◽

Energy Dissipation ◽

Cellular Automata ◽

Quantum Dot ◽

Lower Energy ◽

Logical Function ◽

Quantum Dot Cellular Automata ◽

Qca Circuits ◽

Effective Design ◽

Number Of Cells

Quantum Dot Cellular Automata (QCA) is treated as a most promising technology after CMOS techniques. The major advantages of QCA techniques are faster speed, lower energy consumption and smaller size. The implementation of clocks play very big role in the effective design of QCA circuits. In this paper, a QCA circuit is designed using the concept of QCA clocks. The proposed study describes a new method of implementing the logical function with power depletion analysis. The proposed logical function uses total number of 57 cells in which the area of each cell 372 nm2. The energy dissipation in this implementation is 18.79 meV and the total acquired area is 0.192 µm2. The proposed circuit is implemented utilizing QCA Designer. The proposal is excellent in the realization of nano-scale computing with minimal power utilization. The results are compared with the existing approaches and improvements of 6% in the area required and 7% in the number of cells are achieved

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Design of Falling-Edge Triggered T Flip-Flop based on Quantum-Dot Cellular Automata

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i4.4.19599 ◽

2018 ◽

Vol 7 (4.4) ◽

pp. 19 ◽

Cited By ~ 1

Author(s):

Young Won You ◽

Jun Cheol Jeon

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Pulse Generator ◽

Essential Element ◽

Clock Pulse ◽

Flip Flop ◽

Quantum Dot Cellular Automata ◽

Clock Pulse Generator ◽

Qca Circuits

A T flip-flop, which is an essential element of a counter, has been proposed as various types of quantum-dot cellular automata (QCA) circuits, but practicality is not expected because there is no clock in circuit. A T flip-flop is a circuit which outputs value changing in synchronization with the rising or falling edge of a clock. In a QCA circuit, a clock pulse generator outputs the time at which the clock changes and it is required for the circuit. In this paper, we propose a falling-edge triggered T flip-flop based on QCA.

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Design and Simulation of Reliable and Fast Nanomagnetic Conservative Quantum-dot Cellular Automata (NCQCA) Gate

10.21203/rs.3.rs-412497/v1 ◽

2021 ◽

Author(s):

Ali Akbar Dadjouyan ◽

Samira Sayedsalehi ◽

Reza Faghih Mirzaee ◽

Somayyeh Jafarali Jassbi

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Physical Simulation ◽

Basic Block ◽

Quantum Dot Cellular Automata ◽

Geometrical Properties ◽

Fredkin Gate ◽

Simulation And Evaluation ◽

Qca Circuits ◽

Conservative Logic

Abstract Nanomagnetic Logic (NML) is a promising candidate for the real implementation of quantum-dot cellular automata (QCA) circuits and can be a proper alternative or complement to CMOS circuits. Like any other nanoscale technologies, NML circuits are also subject to fabrication variations. These variations along with fluctuations caused by thermal noise can affect the performance of these circuits. Therefore, design of NML circuits with high testability is an absolute necessity. Circuits based on conservative logic are inherently testable because of their specific properties. In this paper, considering the physical and geometrical properties of nanomagnets, a nanomagnetic conservative quantum-dot cellular automata (NCQCA) gate is designed and evaluated. This circuit can be used as the basic block for the realization of more complex conservative NML circuits. To implement this circuit, the design of the clocked nanomagnetic majority gate is also provided. The OOMMF physical simulation tool is used for simulation and evaluation. The results show the correct functionality of the proposed conservative gate at room temperature. It operates about 34% faster than the NML Fredkin gate. Moreover, the NML version of the conventional Fredkin gate takes 90% more area than the proposed design.

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