Design and implementation of Dual-Port Memory

Multiport memory cell using a dual-port memory cell provides required access to multi-processor-based applications. Simultaneous access can be provided using two-pass transistors, pair of bit lines, and a word line. Using specific word lines and bit lines of SRAM cell access can be provided by using dual ports memory. The single address of a memory cell can be accessed at a time during each clock pulse using single-port SRAM this drawback can be overcome by using dual-port RAM which supports concurrent read or writes access at different addresses. Efficiency is improved by using dual-port RAM. Each processor can be made to operate at different clock frequencies thereby dual-port RAM will not have any limitations of access between the two ports.

EMI Reduction of PFC Rectifier and LLC Converter with Automatic Output Ripple Improvement

This paper proposes the method of the Electro-Magnetic Interference (EMI) noise reduction of the AC-DC rectifiers and the DC-DC converters with the insulated transformers. For the Power Factor Correction (PFC) rectifier, the power factor is the most important item, but the EMI noise emitted from the clock pulse is not remarked. For the DC-DC converters such as the forward converter, the efficiency is the most important. We have focused on the EMI noise reduction for the PFC rectifier and insulated DC-DC converters with the frequency modulation of the clock pulses. First, the spectrum level of the clock pulse is introduced to be much reduced by shaking the clock frequency for the PFC rectifier and the forward converter. Next, we have investigated the EMI reduction of the LLC converter whose operating frequency varies to make the output voltage stable. It is difficult to modify the operating frequency to reduce the EMI noise. We have investigated to reduce the EMI noise by shaking the duty ratio of the resonant signals for the LLC converter. In this case, the output voltage ripple is increased by much EMI noise reduction. Finally, the technology to stabilize the increased ripple is introduced.

Automatic Current Balance for Multi-Phase Switching Converters with Ripple Control or Soft Switch

This paper proposes a new multi-phase switching converter with atuotomatic current barance technique. It is well-known that the multi-phase switching converter is suitable to handle large output current with small output voltage ripple for the buck converters which use the clock pulse. This paper investigates a multi-phase controlled method for the ripple-controlled converters and the soft switching converters, that use no clock pulse; for this reason, these converters are difficult to realize multi-phase converter configurations. There are some multi-phase hysteretic controlled converters; they utilize a main clock generator or an external sub-clock pulse, which has the master-slave synchronization method. But it is difficult to respond to a frequency change of the master converter. These multi-phase converters have not considered the imbalance among phase currents caused by variations of inductors and semiconductor switches in the power stage. For the commercialized multi-phase Voltage Regulating Modules (VRMs), the inductors and the semiconductor switches are selected to adjust the balance among the phase currents. However, there is no multi-phase soft switching converter.Then we have developed the multi-phase ripple-controlled converter and the multi-phase soft switching converter with the technique of detecting 180-degree from the variable operating frequency of the main converter. Moreover, in these converters, there appears the current imbalance because of the element variations among inductors and capacitors, if some cares are not taken there. Then we have developed the automatic correction for the current imbalance by modifying the width of the Constant On Time (COT) pulse or modifying the slope of the saw-tooth signal.

Reduction of Inrush Current in a Shockwave Non-Thermal Food Processing System Using an Exponential Clock Pulse Generator

Recently, shockwave food processing is drawing much attention as a low-cost non-thermal food process technique. In shockwave non-thermal food processing, underwater shockwaves are generated by a high voltage generator. Therefore, high inrush currents and high voltage stress on circuit components significantly reduce the reliability and life expectancy of the circuit. However, to the best of our knowledge, stress reduction techniques and their experimental verification have not been studied yet in the shockwave non-thermal food processing system. In this paper, we propose a stress reduction technique for the shockwave non-thermal food processing system and investigate the effectiveness of the proposed technique experimentally. To achieve high reliability and life expectancy, a new high voltage multiplier with an exponential clock pulse generator is proposed for the shockwave non-thermal food processing system. By slowing down the rate at which the capacitors charge in the high voltage multiplier, the exponential clock pulse generator significantly reduces the inrush current. Furthermore, to perform shockwave non-thermal food processing continuously at a lower voltage level, we present a new electrode with a reset mechanism for wire electric discharge (WED), where a square-shaped metal wire swings on a hinge in the proposed electrode. The proposed electrode enables not only shockwave generation at a lower voltage level but also continuous non-thermal food processing, because the square-shaped metal wire is not melted in the WED process. To confirm the validity of the proposed techniques, some experiments are performed regarding the laboratory prototype of the shockwave non-thermal food processing system. In the performed experiments, reduction of inrush currents and effective food processing are confirmed.

Design of Falling-Edge Triggered T Flip-Flop based on Quantum-Dot Cellular Automata

A T flip-flop, which is an essential element of a counter, has been proposed as various types of quantum-dot cellular automata (QCA) circuits, but practicality is not expected because there is no clock in circuit. A T flip-flop is a circuit which outputs value changing in synchronization with the rising or falling edge of a clock. In a QCA circuit, a clock pulse generator outputs the time at which the clock changes and it is required for the circuit. In this paper, we propose a falling-edge triggered T flip-flop based on QCA.