In a finite state machine (FSM), there is only one active state while the other states are in idle states simultaneously. Thus, only one state is required to power up, the other states can be switched off to save active power. Normally, a backward traversing algorithm is used to label
the power gating cells and extract the enable signals for combinational logic gates in reducing the active power consumption. This conventional power gating technique uses the extracted enable signals to turn ON/OFF these inserted NMOS switches. Then, a power management unit is required to
manage these enable signals and detect the idle periods. The proposed self-power saving technique uses internally generated enable signals from state transitions to control NMOS switches inserted under the ground rail of each state. All internal enable signals are created to activate/deactivate
the machine states at the same time. Based on the next state of the FSM, a decoder creates the enable signals for each state to do power gating in an Automatic Teller Machine (ATM) application. The isolation cell is designed to isolate the current state and next state for retaining data. Simulation
results show the power saving from 31.99% at a WAIT state to 82.87% at a LOCK state, depending on the current state of the finite state machine. On average, the power loss is saved up to 63.2% in the FSM. An overhead area is about 12% compared to the conventional technique while timing overhead
is under 5%.
Finite state machine synthesis with concurrent error detection