An 8 bits, RF UHF-Band DAC based on interleaved bandpass delta sigma modulator assisted by background digital calibration

Integration ◽  
2021 ◽  
Author(s):  
Farshad Aghasharif ◽  
Mohammadreza Malekpour ◽  
Reza Bigdeli ◽  
Pooya Torkzadeh
2012 ◽  
Vol E95.B (7) ◽  
pp. 2257-2265
Author(s):  
Toru KITAYABU ◽  
Mao HAGIWARA ◽  
Hiroyasu ISHIKAWA ◽  
Hiroshi SHIRAI

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 177
Author(s):  
Dongjun Park ◽  
Sungwook Choi ◽  
Jongsun Kim

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.


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