Application specific integrated circuit (ASIC) readout technologies for future ion beam analytical instruments

Author(s):  
Harry J. Whitlow
2018 ◽  
Vol 7 (2.23) ◽  
pp. 464
Author(s):  
Angshuman Khan ◽  
Sudip Halder ◽  
Shubhajit Pal

This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.  


Mathematics ◽  
2020 ◽  
Vol 8 (8) ◽  
pp. 1343
Author(s):  
Hyunjun Kim ◽  
Kyungho Kim ◽  
Hyeokdong Kwon ◽  
Hwajeong Seo

Application-Specific Integrated Circuit (ASIC)-resistant Proof-of-Work (PoW) is widely adopted in modern cryptocurrency. The operation of ASIC-resistant PoW on ASIC is designed to be inefficient due to its special features. In this paper, we firstly introduce a novel ASIC-resistant PoW for low-end microcontrollers. We utilized the measured power trace during the cryptographic function on certain input values. Afterward, the post-processing routine was performed on the power trace to remove the noise. The refined power trace is always constant information depending on input values. By performing the hash function with the power trace, the final output was obtained. This framework only works on microcontrollers and the power trace depends on certain input values, which is not predictable and computed by ASIC.


Author(s):  
D.C. Mayer ◽  
R.J. Ferro ◽  
D.L. Leung ◽  
M.A. Dooley ◽  
J.R. Scarpulla

Abstract Radiation-induced latchup sites in a high-performance commercial application-specific integrated circuit (ASIC) manufactured in a bipolar gate array have been identified using a photoemission (PE) microscope before and after isolating individual circuit elements with a focused ion beam (FIB) system. Latchup sites were determined to be associated with grounded unused resistors and transistors in an emitter-coupled logic (ECL) input buffer. Simulation of the oxide isolation scheme confirmed the presence of pnpn structures at the likely latchup sites. A corrective action to redesign the layouts to disconnect unused resistors and transistors resulted in successful elimination of latchup in the ECL buffers.


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