A sonar ring with continuous matched filtering and dynamically switched templates

Robotica ◽  
2011 ◽  
Vol 30 (6) ◽  
pp. 891-912 ◽  
Author(s):  
Damien C. Browne ◽  
Lindsay Kleeman
Keyword(s):  
Field Programmable Gate Array ◽  
Pulse Shape ◽  
Arrival Time ◽  
Matched Filter ◽  
Sine Wave ◽  
Matched Filtering ◽  
Low Latency ◽  
Field Programmable ◽  
Sonar Sensor ◽  
Template Selection

SUMMARYMatched filtering optimally estimates the arrival time for a sonar sensor by correlating received signals with templates. This paper presents a sonar ring with continuous matched filtering on 48 receiver channels sampled at 500kHz. The design dynamically switches the matched filter templates to account for pulse shape variations with range. To achieve real-time, low-latency and optimal performance, processing is implemented on an field-programmable gate array (FPGA) transmitting sonar pulses (2 periods of a 45kHz sine wave) at repetition rate of 30-Hz to 5.7-m range. The paper describes the removal of secondary peaks of the correlation output of matched filtering and template selection. Results include sonar maps, accuracy measurements and localization of weak targets.

An Accelerator for Decoding Market Data Based on FPGA

2019 ◽  
Vol 28 (03) ◽  
pp. 1950050
Author(s):  
Yuhao Dou ◽  
Yisu Zhou ◽  
Bo Xin
Keyword(s):  
Information Exchange ◽  
Field Programmable Gate Array ◽  
Financial Information ◽  
Low Latency ◽  
Market Data ◽  
Field Programmable ◽  
Leading Position ◽  
Average Latency ◽  
The Cost ◽  
Securities Trading

In securities trading, low latency helps investors take the leading position in the market. Conventionally, market data is decoded with software running on general computers. However, the serial structure of software and complex operating system scheduling cause high latency. This paper designs an accelerator for decoding market data based on field-programmable gate array (FPGA). We propose a pipeline in the accelerator, where every part works independently and parallelly. Furthermore, we present a mechanism for encoding templates, which avoids reconstructing the accelerator and decreases the cost when the template is renewed. We evaluate this accelerator with real Financial Information eXchange (FIX) messages and FIX Adapting for Streaming (FAST) templates, attaining an average latency of 447[Formula: see text]ns.

A double refresh rate sonar ring with FPGA-based continuous matched filtering

Robotica ◽  
2011 ◽  
Vol 30 (7) ◽  
pp. 1051-1062 ◽  
Author(s):  
Damien C. Browne ◽  
Lindsay Kleeman
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Matched Filtering ◽  
Interference Rejection ◽  
Random Set ◽  
Refresh Rate ◽  
Maximum Range ◽  
Field Programmable ◽  
Match Filtering ◽  
Signal Processors

SUMMARYExisting sonar rings are limited in their refresh rate to the transmit echo rate, that is, waiting for maximum range echoes to arrive before transmitting again. This paper presents a sonar ring refreshing at 60 Hz for 5.7-m range, which is twice the transmit echo rate, and this leads to lower latency, denser measurements. Two custom Field Programmable Gate Array signal processors provide real time continuous match filtering with dynamic templates. A new method is implemented to select the transmit time from a random set based on minimizing interference. Experiments demonstrate the increased refresh rate, interference rejection, and maps generated by the sonar ring.

scholarly journals High Performance and Low Latency ECC Processor for Cryptography

2021 ◽  
pp. 24-30
Author(s):  
Mohan Rao Thokala
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Low Latency ◽  
Data Dependency ◽  
Drastic Reduction ◽  
Point Multiplication ◽  
Field Programmable ◽  
Xilinx Fpga

Elliptic curve cryptography processor implemented for point multiplication on field programmable gate array. Segmented pipelined full-precision multiplier is used to reduce the latency and also data dependency can be avoided by modifying Lopez-Dahab Montgomery PM Algorithm, results in drastic reduction in the number of clock cycles required. The proposed ECC processor is implemented on Xilinx FPGA families i.e. virtex-4, vitrtex-5, virtex-7.single and three multiplier based designs show the fastest performance compared with reported work individually. Our three multiplier based ECC processor implementation is taking the lowest number of clock cycles on FPGA based design processor.

Low-Latency, Small-Area FPGA Implementation of the Advanced Encryption Standard Algorithm

2013 ◽  
Vol 4 (1) ◽  
pp. 56-77
Author(s):  
Hoang Trang ◽  
Nguyen Van Loi
Keyword(s):  
Field Programmable Gate Array ◽  
Small Area ◽  
Fpga Implementation ◽  
Advanced Encryption Standard ◽  
Low Latency ◽  
Aes Algorithm ◽  
Look Up Table ◽  
Field Programmable ◽  
Encryption Decryption ◽  
Federal Information Processing Standard

This paper presents a Field-Programmable Gate Array (FPGA) implementation of an Advanced Encryption Standard (AES) algorithm using approach of combination iterative looping and Look-Up Table (LUT)-based S-box with block and key size of 128 bits. Modifications in the way of loading data out in AES encryption/decryption, loading key_expansion in Key_Expansion blocks are also proposed. The design is tested with the sample vectors provided by Federal Information Processing Standard (FIPS) 197. The design is implemented on APEX20KC Altera’s FPGA and on Virtex XCV600 Xilinx’s FPGA. For all the authors’ proposals, they are found to be very simple in FPGA-based architecture implementation, better in low latency, and small area, but large in memory, moderate throughput.

Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

2008 ◽  
Author(s):  
Michael Wirthlin ◽  
Brent Nelson ◽  
Brad Hutchings ◽  
Peter Athanas ◽  
Shawn Bohner
Keyword(s):  
Field Programmable Gate Array ◽  
Fpga Design ◽  
Design Methodologies ◽  
Field Programmable ◽  
Gate Array
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