Low-Latency, Small-Area FPGA Implementation of the Advanced Encryption Standard Algorithm

2013 ◽  
Vol 4 (1) ◽  
pp. 56-77
Author(s):  
Hoang Trang ◽  
Nguyen Van Loi
Keyword(s):  
Field Programmable Gate Array ◽  
Small Area ◽  
Fpga Implementation ◽  
Advanced Encryption Standard ◽  
Low Latency ◽  
Aes Algorithm ◽  
Look Up Table ◽  
Field Programmable ◽  
Encryption Decryption ◽  
Federal Information Processing Standard

This paper presents a Field-Programmable Gate Array (FPGA) implementation of an Advanced Encryption Standard (AES) algorithm using approach of combination iterative looping and Look-Up Table (LUT)-based S-box with block and key size of 128 bits. Modifications in the way of loading data out in AES encryption/decryption, loading key_expansion in Key_Expansion blocks are also proposed. The design is tested with the sample vectors provided by Federal Information Processing Standard (FIPS) 197. The design is implemented on APEX20KC Altera’s FPGA and on Virtex XCV600 Xilinx’s FPGA. For all the authors’ proposals, they are found to be very simple in FPGA-based architecture implementation, better in low latency, and small area, but large in memory, moderate throughput.

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

scholarly journals VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

2021 ◽  
Vol 14 (1) ◽  
pp. 22-31
Author(s):  
Kommalapati Monica ◽  
◽  
Dereddy Anuradha ◽  
Syed Rasheed ◽  
Barnala Shereesha ◽  
...  
Keyword(s):  
Power Consumption ◽  
Field Programmable Gate Array ◽  
Finite Impulse Response ◽  
Research Work ◽  
Industrial Applications ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Look Up Table ◽  
Field Programmable ◽  
Wallace Tree Multiplier

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

An Accelerator for Decoding Market Data Based on FPGA

2019 ◽  
Vol 28 (03) ◽  
pp. 1950050
Author(s):  
Yuhao Dou ◽  
Yisu Zhou ◽  
Bo Xin
Keyword(s):  
Information Exchange ◽  
Field Programmable Gate Array ◽  
Financial Information ◽  
Low Latency ◽  
Market Data ◽  
Field Programmable ◽  
Leading Position ◽  
Average Latency ◽  
The Cost ◽  
Securities Trading

In securities trading, low latency helps investors take the leading position in the market. Conventionally, market data is decoded with software running on general computers. However, the serial structure of software and complex operating system scheduling cause high latency. This paper designs an accelerator for decoding market data based on field-programmable gate array (FPGA). We propose a pipeline in the accelerator, where every part works independently and parallelly. Furthermore, we present a mechanism for encoding templates, which avoids reconstructing the accelerator and decreases the cost when the template is renewed. We evaluate this accelerator with real Financial Information eXchange (FIX) messages and FIX Adapting for Streaming (FAST) templates, attaining an average latency of 447[Formula: see text]ns.

AES Enhanced by Output Feedback Block Mode Operation

2020 ◽  
Vol 1 (1) ◽  
pp. 11-22
Author(s):  
Asaad A. Hani
Keyword(s):  
Output Feedback ◽  
Data Security ◽  
New Technology ◽  
Advanced Encryption Standard ◽  
The Internet ◽  
Secret Key ◽  
Aes Algorithm ◽  
Mode Operation ◽  
Federal Information Processing Standard ◽  
Exclusive Or

There is a great research in the field of data security these days. Storing information digitally in the cloud and transferring it over the internet proposes risks of disclosure and unauthorized access; thus, users, organizations, and businesses are adapting new technology and methods to protect their data from breaches. In this paper, we introduce a method to provide higher security for data transferred over the internet, or information based in the cloud. The introduced method for the most part depends on the Advanced Encryption Standard (AES) algorithm, which is currently the standard for secret key encryption. A standardized version of the algorithm was used by The Federal Information Processing Standard 197 called Rijndael for the AES. The AES algorithm processes data through a combination of exclusive-OR operations (XOR), octet substitution with an S-box, row and column rotations, and MixColumn operations. The fact that the algorithm could be easily implemented and run on a regular computer in a reasonable amount of time made it highly favorable and successful. In this paper, the proposed method provides a new dimension of security to the AES algorithm by securing the key itself such that even when the key is disclosed; the text cannot be deciphered. This is done by enciphering the key using Output Feedback Block Mode Operation. This introduces a new level of security to the key in a way, in which deciphering the data requires prior knowledge of the key and the algorithm used to encipher the key for the purpose of deciphering the transferred text.

scholarly journals Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

2019 ◽  
Vol 29 (09) ◽  
pp. 2050136
Author(s):  
Yuuki Tanaka ◽  
Yuuki Suzuki ◽  
Shugang Wei
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Number System ◽  
Logic Circuit ◽  
Fpga Implementation ◽  
Number Representation ◽  
Representation System ◽  
Representation Systems ◽  
Field Programmable ◽  
Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

Memristor Oscillators and its FPGA Implementation

2011 ◽  
Vol 383-390 ◽  
pp. 6992-6997 ◽  
Author(s):  
Ai Xue Qi ◽  
Cheng Liang Zhang ◽  
Guang Yi Wang
Keyword(s):  
Numerical Simulation ◽  
Chaotic System ◽  
Field Programmable Gate Array ◽  
Chaotic Attractor ◽  
Hardware Implementation ◽  
Fpga Implementation ◽  
Experimental Results ◽  
Linear Resistance ◽  
Non Linear ◽  
Field Programmable

This paper presents a method that utilizes a memristor to replace the non-linear resistance of typical Chua’s circuit for constructing a chaotic system. The improved circuit is numerically simulated in the MATLAB condition, and its hardware implementation is designed using field programmable gate array (FPGA). Comparing the experimental results with the numerical simulation, the two are the very same, and be able to generate chaotic attractor.

A sonar ring with continuous matched filtering and dynamically switched templates

Robotica ◽  
2011 ◽  
Vol 30 (6) ◽  
pp. 891-912 ◽  
Author(s):  
Damien C. Browne ◽  
Lindsay Kleeman
Keyword(s):  
Field Programmable Gate Array ◽  
Pulse Shape ◽  
Arrival Time ◽  
Matched Filter ◽  
Sine Wave ◽  
Matched Filtering ◽  
Low Latency ◽  
Field Programmable ◽  
Sonar Sensor ◽  
Template Selection

SUMMARYMatched filtering optimally estimates the arrival time for a sonar sensor by correlating received signals with templates. This paper presents a sonar ring with continuous matched filtering on 48 receiver channels sampled at 500kHz. The design dynamically switches the matched filter templates to account for pulse shape variations with range. To achieve real-time, low-latency and optimal performance, processing is implemented on an field-programmable gate array (FPGA) transmitting sonar pulses (2 periods of a 45kHz sine wave) at repetition rate of 30-Hz to 5.7-m range. The paper describes the removal of secondary peaks of the correlation output of matched filtering and template selection. Results include sonar maps, accuracy measurements and localization of weak targets.

Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array

2016 ◽  
Vol 10 (3) ◽  
pp. 163-172 ◽  
Author(s):  
Zarrin Tasnim Sworna ◽  
Mubin UlHaque ◽  
Nazma Tara ◽  
Hafiz Md. Hasan Babu ◽  
Ashis Kumar Biswas
Keyword(s):  
Low Power ◽  
Field Programmable Gate Array ◽  
Look Up Table ◽  
Field Programmable ◽  
Decimal Adder ◽  
Gate Array ◽  
Area Efficient

scholarly journals Technology Mapping of FSM Oriented to LUT-Based FPGA

2020 ◽  
Vol 10 (11) ◽  
pp. 3926
Author(s):  
Marcin Kubica ◽  
Dariusz Kania
Keyword(s):  
Field Programmable Gate Array ◽  
Finite State Machine ◽  
Synthesis Method ◽  
Technology Mapping ◽  
Look Up Table ◽  
Finite State ◽  
Field Programmable ◽  
Simultaneous Synthesis ◽  
Transition Block ◽  
Logic Blocks

The main purpose of the paper is to present technology mapping of FSM (finite state machine) oriented to LUT (look-up table)-based FPGA (field-programmable gate array). The combinational part of an automaton, which consists of a transition block and an output block, was mapped in LUT-based logic blocks. In the paper, the idea of carrying out the combinational part of FSM was presented and leads to the reduction of the number of LUTs needed to carry out an automaton. The essence of this method is a simultaneous synthesis of the whole combinational block described in the form of multi-output function. The proposed idea makes it possible to conduct decomposition that may enable to share logic blocks, which can lead to the reduction of using resources of FPGA. The decomposition process was conducted using the analyzed DECOMP system. The effectiveness of the proposed idea of the FSM description was also confirmed by conducting decomposition with the usage of the ABC system. The obtained results prove the efficiency of the proposed synthesis method of FSM in comparison with the separate synthesis of a transition block and an output block.

FPGA Implementation of a Soft Sensor for the Estimation of the Freezing Point of Kerosene

2009 ◽  
Author(s):  
Riccardo Caponetto ◽  
Giovanni Dongola ◽  
Antonio Gallo ◽  
Maria Gabriella Xibilia
Keyword(s):  
Neural Networks ◽  
Field Programmable Gate Array ◽  
Freezing Point ◽  
Industrial Process ◽  
Soft Sensor ◽  
Fpga Implementation ◽  
Distillation Unit ◽  
Atmospheric Distillation ◽  
New Strategy ◽  
Field Programmable

A new strategy to realize an FPGA implementation of a soft sensor for an industrial process is proposed. The proposed approach is based on the integration on Field Programmable Gate Array (FPGA) of a neural networks. The proposed method has been applied to develop a soft sensor for the estimation of the freezing point of kerosene in an atmospheric distillation unit (topping) working in a refinery in Sicily, Italy.

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