Scalable processes for fabricating non-volatile memory devices using self-assembled 2D arrays of gold nanoparticles as charge storage nodes

Nanoscale ◽  
2011 ◽  
Vol 3 (11) ◽  
pp. 4575 ◽  
Author(s):  
Girish Muralidharan ◽  
Navakanta Bhat ◽  
Venugopal Santhanam
Keyword(s):  
Gold Nanoparticles ◽  
Charge Storage ◽  
Memory Devices ◽  
Non Volatile Memory ◽  
2D Arrays ◽  
Volatile Memory ◽  
Self Assembled

Enhancing charge-storage capacity of non-volatile memory devices using template-directed assembly of gold nanoparticles

Nanoscale ◽  
2012 ◽  
Vol 4 (7) ◽  
pp. 2296 ◽  
Author(s):  
Raju Kumar Gupta ◽  
Sivashankar Krishnamoorthy ◽  
Damar Yoga Kusuma ◽  
Pooi See Lee ◽  
M. P. Srinivasan
Keyword(s):  
Gold Nanoparticles ◽  
Storage Capacity ◽  
Directed Assembly ◽  
Charge Storage ◽  
Memory Devices ◽  
Non Volatile Memory ◽  
Volatile Memory

Charge Storage Behaviors of Ge Nanocrystals Embedded in SiO2 for the Application in Non-Volatile Memory Devices

2010 ◽  
Vol 10 (7) ◽  
pp. 4517-4521 ◽  
Author(s):  
M. Yang ◽  
T. P. Chen ◽  
J. I. Wong ◽  
Y. Liu ◽  
Ampere A. Tseng ◽  
...  
Keyword(s):  
Charge Storage ◽  
Memory Devices ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Ge Nanocrystals

scholarly journals Flash memory devices with metal floating gate/metal nanocrystals as the charge storage layer: A status review

2020 ◽  
Vol 33 (2) ◽  
pp. 155-167
Author(s):  
Renu Rajput ◽  
Rakesh Vaid
Keyword(s):  
Flash Memory ◽  
Floating Gate ◽  
Tunneling Effect ◽  
Charge Storage ◽  
Memory Devices ◽  
Metal Nanocrystals ◽  
Operation Speed ◽  
Research Activities ◽  
Non Volatile Memory ◽  
Volatile Memory

Traditional flash memory devices consist of Polysilicon Control Gate (CG) - Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) - Polysilicon Floating Gate (FG) - Silicon Oxide (Tunnel dielectric) - Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect. Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer.

Resistive switching characteristics of all-solution-based Ag/TiO2/Mo-doped In2O3devices for non-volatile memory applications

2016 ◽  
Vol 4 (46) ◽  
pp. 10967-10972 ◽  
Author(s):  
Sujaya Kumar Vishwanath ◽  
Jihoon Kim
Keyword(s):  
Resistive Switching ◽  
Retention Time ◽  
Elevated Temperatures ◽  
Switching Behavior ◽  
Memory Devices ◽  
Bipolar Switching ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Switching Characteristics ◽  
Memory Applications

The all-solution-based memory devices demonstrated excellent bipolar switching behavior with a high resistive switching ratio of 103, excellent endurance of more than 1000 cycles, stable retention time greater than 104s at elevated temperatures, and fast programming speed of 250 ns.

Fluorenone/carbazole based bipolar small molecules for non-volatile memory devices

2020 ◽  
Vol 78 ◽  
pp. 105584 ◽  
Author(s):  
Jia-Qin Yang ◽  
Li-Yu Ting ◽  
Ruopeng Wang ◽  
Jing-Yu Mao ◽  
Yi Ren ◽  
...  
Keyword(s):  
Small Molecules ◽  
Memory Devices ◽  
Non Volatile Memory ◽  
Volatile Memory

scholarly journals Comparing domain wall synapse with other non volatile memory devices for on-chip learning in analog hardware neural network

AIP Advances ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 025111 ◽  
Author(s):  
Divya Kaushik ◽  
Utkarsh Singh ◽  
Upasana Sahu ◽  
Indu Sreedevi ◽  
Debanjan Bhowmik
Keyword(s):  
Neural Network ◽  
Domain Wall ◽  
Memory Devices ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
On Chip ◽  
Hardware Neural Network

Graphene Based Non-Volatile Memory Devices

2014 ◽  
Vol 26 (31) ◽  
pp. 5496-5503 ◽  
Author(s):  
Xiaomu Wang ◽  
Weiguang Xie ◽  
Jian-Bin Xu
Keyword(s):  
Memory Devices ◽  
Non Volatile Memory ◽  
Volatile Memory
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