scholarly journals Flash memory devices with metal floating gate/metal nanocrystals as the charge storage layer: A status review

2020 ◽  
Vol 33 (2) ◽  
pp. 155-167
Author(s):  
Renu Rajput ◽  
Rakesh Vaid

Traditional flash memory devices consist of Polysilicon Control Gate (CG) - Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) - Polysilicon Floating Gate (FG) - Silicon Oxide (Tunnel dielectric) - Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect. Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer.

2004 ◽  
Vol 830 ◽  
Author(s):  
Cesare Clementi ◽  
Roberto Bez

ABSTRACTThe most relevant phenomenon of this last decade in the field of semiconductor memories has been the explosive growth of the Flash memory market, driven by cellular phones and other types of electronic portable equipments (palm top, mobile PC, mp3 audio player, digital camera and so on). Moreover, in the coming years portable systems will ask even more non volatile memories either with high density and very high writing throughput for data storage application, or with fast random access for code execution in place. The strong consolidated know-how (more than ten years of experience), the flexibility and the cost make the floating gate Flash Memory a largely utilized, well-consolidated and mature technology for most of the non-volatile memory application. Today Flash sales represent a considerable amount of the overall semiconductor market.Nowadays two of the several cell architecture proposed up to now can be considered as industry standard: the common ground NOR Flash that due to its versatility is addressing both the code and data storage segments and the NAND Flash, optimized for the data storage market.The exploitation of the multilevel approach at each technology node allows the increase of the memory efficiency, about doubling the density at the same chip size, widening the application range and reducing the cost per bit.In this paper the main issues related to both NOR and NAND Flash memory technology will be summarized, with the aim of describing both the basic functionality of the memory cell and the main cell architecture today consolidated. Both cells are basically a floating-gate MOS transistor, programmed by channel hot electron (NOR) or by Fowler-Nordheim tunneling (NAND) and erased by Fowler-Nordheim tunnel. The main reliability properties, charge retention and endurance, are presented, together with some comments on the basic physical mechanisms responsible for.A couple of innovative approaches to floating gate cell evolution, namely nanocrystal memory and 3-D cell will be described.Finally the Flash cell scaling issues will be covered, pointing out the main challenges. The Flash cell scaling has been demonstrated to be really possible and to be able to follow the Moore's law down to the 90 nm technology generations. The technology development and the consolidated know-how are expected to sustain the scaling trend down to the 50 nm technology node and below as forecasted by the ITRS roadmap.


2010 ◽  
Vol 10 (7) ◽  
pp. 4517-4521 ◽  
Author(s):  
M. Yang ◽  
T. P. Chen ◽  
J. I. Wong ◽  
Y. Liu ◽  
Ampere A. Tseng ◽  
...  

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1101
Author(s):  
Muhammad Naqi ◽  
Nayoung Kwon ◽  
Sung Hyeon Jung ◽  
Pavan Pujar ◽  
Hae Won Cho ◽  
...  

Non-volatile memory (NVM) devices based on three-terminal thin-film transistors (TFTs) have gained extensive interest in memory applications due to their high retained characteristics, good scalability, and high charge storage capacity. Herein, we report a low-temperature (<100 °C) processed top-gate TFT-type NVM device using indium gallium zinc oxide (IGZO) semiconductor with monolayer gold nanoparticles (AuNPs) as a floating gate layer to obtain reliable memory operations. The proposed NVM device exhibits a high memory window (ΔVth) of 13.7 V when it sweeps from −20 V to +20 V back and forth. Additionally, the material characteristics of the monolayer AuNPs (floating gate layer) and IGZO film (semiconductor layer) are confirmed using transmission electronic microscopy (TEM), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) techniques. The memory operations in terms of endurance and retention are obtained, revealing highly stable endurance properties of the device up to 100 P/E cycles by applying pulses (±20 V, duration of 100 ms) and reliable retention time up to 104 s. The proposed NVM device, owing to the properties of large memory window, stable endurance, and high retention time, enables an excellent approach in futuristic non-volatile memory technology.


Nanoscale ◽  
2012 ◽  
Vol 4 (7) ◽  
pp. 2296 ◽  
Author(s):  
Raju Kumar Gupta ◽  
Sivashankar Krishnamoorthy ◽  
Damar Yoga Kusuma ◽  
Pooi See Lee ◽  
M. P. Srinivasan

2019 ◽  
Vol 14 (9) ◽  
pp. 1195-1214 ◽  
Author(s):  
Afiq Hamzah ◽  
Hilman Ahmad ◽  
Michael Loong Peng Tan ◽  
N. Ezaila Alias ◽  
Zaharah Johari ◽  
...  

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