High performance, reduced complexity programmable RNS-FPL merged FIR filters

2002 ◽  
Vol 38 (4) ◽  
pp. 199 ◽  
Author(s):  
J. Ramírez ◽  
U. Meyer-Baese
Keyword(s):  
High Performance ◽  
Fir Filters ◽  
Reduced Complexity

Radiation Transport Simulation Results Assessment Through Comparison With Reduced Complexity Analytic and Computational Models (LA-UR-20-22342)

2020 ◽  
Author(s):  
Tyler J. Remedes ◽  
Scott D. Ramsey ◽  
Joseph H. Schmidt ◽  
James Baciak
Keyword(s):  
Spatial Distribution ◽  
Neutron Flux ◽  
High Performance ◽  
Computational Models ◽  
Radiation Transport ◽  
Complex Model ◽  
Spent Fuel ◽  
Fundamental Physics ◽  
Analysis Process ◽  
Reduced Complexity

Abstract In the past when faced with solving a non-tractable problem, scientists would make tremendous efforts to simplify these problems while preserving fundamental physics. Solutions to the simplified models provided insight into the original problem. Today, however, the affordability of high-performance computing has inverted the process for analyzing complex problems. In this paradigm, results from detailed computational scenarios can be better assessed by “building down” the complex model through simple models rooted in the fundamental or essential phenomenology. This work demonstrates how the analysis of the neutron flux spatial distribution behavior within a simulated Holtec International HI-STORM 100 spent fuel cask is enhanced through reduced complexity analytic and computational modeling. This process involves identifying features in the neutron flux spatial distribution and determining the cause of each using reduced complexity computational and/or analytic model. Ultimately, confidence in the accuracy of the original simulation result is gained through this analysis process.

Efficient FIR Filter Architecture using FPGA

2020 ◽  
Vol 13 (1) ◽  
pp. 91-98
Author(s):  
Ahmed K. Jameil ◽  
Yassir A. Ahmed ◽  
Saad Albawi
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Performance ◽  
Finite Impulse Response ◽  
Low Complexity ◽  
Fir Filter ◽  
Fir Filters ◽  
Filter Architecture ◽  
Circuit Techniques ◽  
And Performance

Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

scholarly journals Significance of Logic Synthesis in FPGA-Based Design of Image and Signal Processing Systems

2008 ◽  
pp. 265-283 ◽  
Author(s):  
Mariusz Rawski ◽  
Henry Selvaraj ◽  
Bogdan J. Falkowski ◽  
Tadeusz Luba
Keyword(s):  
Signal Processing ◽  
High Performance ◽  
Digital Filters ◽  
Logic Synthesis ◽  
General Purpose ◽  
Digital Systems ◽  
Fir Filters ◽  
Distributed Arithmetic ◽  
Embedded Dsp ◽  
Very High

This chapter, taking FIR filters as an example, presents the discussion on efficiency of different implementation methodologies of DSP algorithms targeting modern FPGA architectures. Nowadays, programmable technology provides the possibility to implement digital systems with the use of specialized embedded DSP blocks. However, this technology gives the designer the possibility to increase efficiency of designed systems by exploitation of parallelisms of implemented algorithms. Moreover, it is possible to apply special techniques, such as distributed arithmetic (DA). Since in this approach, general-purpose multipliers are replaced by combinational LUT blocks, it is possible to construct digital filters of very high performance. Additionally, application of the functional decomposition-based method to LUT blocks optimization, and mapping has been investigated. The chapter presents results of the comparison of various design approaches in these areas.

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