A flexible implementation of high-performance FIR filters on Xilinx FPGAs

1998 ◽  
pp. 441-445 ◽  
Author(s):  
Tien-Toan Do ◽  
Holger Kropp ◽  
Carsten Reuter ◽  
Peter Pirsch
Keyword(s):  
High Performance ◽  
Fir Filters

Efficient FIR Filter Architecture using FPGA

2020 ◽  
Vol 13 (1) ◽  
pp. 91-98
Author(s):  
Ahmed K. Jameil ◽  
Yassir A. Ahmed ◽  
Saad Albawi
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Performance ◽  
Finite Impulse Response ◽  
Low Complexity ◽  
Fir Filter ◽  
Fir Filters ◽  
Filter Architecture ◽  
Circuit Techniques ◽  
And Performance

Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

High performance, reduced complexity programmable RNS-FPL merged FIR filters

2002 ◽  
Vol 38 (4) ◽  
pp. 199 ◽  
Author(s):  
J. Ramírez ◽  
U. Meyer-Baese
Keyword(s):  
High Performance ◽  
Fir Filters ◽  
Reduced Complexity

scholarly journals Significance of Logic Synthesis in FPGA-Based Design of Image and Signal Processing Systems

2008 ◽  
pp. 265-283 ◽  
Author(s):  
Mariusz Rawski ◽  
Henry Selvaraj ◽  
Bogdan J. Falkowski ◽  
Tadeusz Luba
Keyword(s):  
Signal Processing ◽  
High Performance ◽  
Digital Filters ◽  
Logic Synthesis ◽  
General Purpose ◽  
Digital Systems ◽  
Fir Filters ◽  
Distributed Arithmetic ◽  
Embedded Dsp ◽  
Very High

This chapter, taking FIR filters as an example, presents the discussion on efficiency of different implementation methodologies of DSP algorithms targeting modern FPGA architectures. Nowadays, programmable technology provides the possibility to implement digital systems with the use of specialized embedded DSP blocks. However, this technology gives the designer the possibility to increase efficiency of designed systems by exploitation of parallelisms of implemented algorithms. Moreover, it is possible to apply special techniques, such as distributed arithmetic (DA). Since in this approach, general-purpose multipliers are replaced by combinational LUT blocks, it is possible to construct digital filters of very high performance. Additionally, application of the functional decomposition-based method to LUT blocks optimization, and mapping has been investigated. The chapter presents results of the comparison of various design approaches in these areas.

scholarly journals A High-Performance FIR filter Architecture for Reconfigurable Applications

2019 ◽  
pp. 420-424
Author(s):  
R. Yerriswamy ◽  
D. Vishnu Vardhan ◽  
Sankar Lal Sharma
Keyword(s):  
High Performance ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Flow Diagram ◽  
Fir Filters ◽  
Significant Saving ◽  
Project Analysis ◽  
Complex Design ◽  
Direct Form ◽  
Filter Architecture

Transpose form finite-impulse response (FIR) filters are characteristically pipelined and support multiple constant multiplications (MCM) procedure that results in significant saving of calculation. However, transpose form configuration does not specifically support the block performing not like direct-form configuration. In this paper, we investigate the possibility of realization of block FIR filter in transpose shape configuration for area-delay efficient realization of huge order FIR filters for both fixed applications. Based on a detailed computational investigation of transpose form configuration of FIR filter, we have derived a flow diagram for transpose shape block FIR filter with reduced register complexity. A detailed block formulation is detailed for transpose form FIR filter. We have inferred a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A reduced-complex design using multiple constant multiplications scheme is also showed for block implementation of fixed FIR filters. The proposed architecture obtains less area, less delay and less power consumption compared with the existing architecture of direct form structure for medium or long filter lengths. For this project analysis for determining area, power and delay it uses Xilinx.

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