Improved Domino logic for high speed design

2003 ◽  
Vol 39 (8) ◽  
pp. 644 ◽  
Author(s):  
Song Jia ◽  
Fei Liu ◽  
Lijiu Ji
Keyword(s):  
High Speed ◽  
Domino Logic ◽  
High Speed Design

High-Speed Digital Domino Logic for Ultra-Low Supply Voltages

2017 ◽  
Vol 36 (12) ◽  
pp. 4774-4788
Author(s):  
Omid Mirmotahari ◽  
Yngvar Berg
Keyword(s):  
High Speed ◽  
Domino Logic ◽  
Supply Voltages

scholarly journals High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

2021 ◽  
pp. 263-269
Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa
Keyword(s):  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Power Performance ◽  
High Speed Design ◽  
Power Delay Product ◽  
Full Swing ◽  
Output Swing ◽  
High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

Design of Low Power and High Speed VLSI Domino Logic Circuit

2018 ◽  
Author(s):  
Praveen J ◽  
Aishwarya Aishwarya ◽  
Jagadish Venkatraman Naik ◽  
Kshithija Kshithija ◽  
Mahesh Biradar
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Circuit ◽  
Domino Logic

A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic

2008 ◽  
Vol 16 (5) ◽  
pp. 594-598 ◽  
Author(s):  
Chua-Chin Wang ◽  
Chi-Chun Huang ◽  
Ching-Li Lee ◽  
Tsai-Wen Cheng
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
High Speed ◽  
Domino Logic ◽  
Dual Threshold Voltage

High-Speed Design of Asymmetric Fabry-Perot Modulators

2005 ◽  
Author(s):  
C.C. Barron ◽  
M. Whitehead ◽  
K.-K. Law ◽  
L.A. Coldren
Keyword(s):  
High Speed ◽  
Fabry Perot ◽  
High Speed Design

scholarly journals Low Power/ High Speed Design in VLSI with the application of Pipelining and Parallel processing

2012 ◽  
Vol 2 (3) ◽  
pp. 96-101
Author(s):  
Shilpa Sathish ◽  
C. Lakshminarayana
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
High Speed ◽  
Vlsi Design ◽  
Percentage Reduction ◽  
High Speed Design

The main objectives of any VLSI design are Power, Delay andArea. Minimizing all the objectives is a challenge in presentsituation but all efforts to achieve one of these can lead to abetter design. This paper proposes an EDA tool for low power/high speed VLSI design, which solves any DFG to estimate thespeed of operation and the percentage reduction in the powerconsumption using pipelining and parallel processing concepts

scholarly journals Implementation of Memory Less Based Low-Complexity CODECS

2016 ◽  
pp. 101-105
Author(s):  
K. Vijayalakshmi ◽  
I.V.G Manohar ◽  
L. Srinivas
Keyword(s):  
High Speed ◽  
Low Complexity ◽  
Brute Force ◽  
Optimal Code ◽  
Coding Scheme ◽  
Forbidden Transition ◽  
Numeral Systems ◽  
High Speed Design ◽  
Crosstalk Avoidance ◽  
Codec Design

In this work, we present a CODEC design for two classes of crosstalk avoidance codes (CACs), forbidden pattern codes (FPCs) and forbidden transition codes (FTCs). Our mapping and coding scheme is based on the Fibonacci numeral system and the mathematical analysis shows that all numbers can be represented by FTF vectors in the Fibonacci numeral system (FNS). The proposed CODEC design is highly efficient, modular and can be easily combined with a bus partitioning technique. We also investigate the implementation issues and our experimental results show that the proposed CODEC complexity is orders of magnitude better compared to the brute force implementation. Compared to the best existing approaches, we achieve a 17% improvement in logic complexity. A high speed design can be achieved through pipelining. In this paper, we generalize the idea in and establish a generic framework for the CODEC design of all classes of CACs based on binary mixed-radix numeral systems. Using this framework, we propose CODECs for OLCs and FPCs with optimal code rates as well as CODECs for FOCs with near-optimal code rates.

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