Energy Efficient Error Resilient Multiplier Using Low-power Compressors

The approximate hardware design can save huge energy at the cost of errors incurred in the design. This article proposes the approximate algorithm for low-power compressors, utilized to build approximate multiplier with low energy and acceptable error profiles. This article presents two design approaches (DA1 and DA2) for higher bit size approximate multipliers. The proposed multiplier of DA1 have no propagation of carry signal from LSB to MSB, resulted in a very high-speed design. The increment in delay, power, and energy are not exponential with increment of multiplier size ( n ) for DA1 multiplier. It can be observed that the maximum combinations lie in the threshold Error Distance of 5% of the maximum value possible for any particular multiplier of size n . The proposed 4-bit DA1 multiplier consumes only 1.3 fJ of energy, which is 87.9%, 78%, 94%, 67.5%, and 58.9% less when compared to M1, M2, LxA, MxA, accurate designs respectively. The DA2 approach is recursive method, i.e., n -bit multiplier built with n/2-bit sub-multipliers. The proposed 8-bit multiplication has 92% energy savings with Mean Relative Error Distance (MRED) of 0.3 for the DA1 approach and at least 11% to 40% of energy savings with MRED of 0.08 for the DA2 approach. The proposed multipliers are employed in the image processing algorithm of DCT, and the quality is evaluated. The standard PSNR metric is 55 dB for less approximation and 35 dB for maximum approximation.

Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware

BIKE is a Key Encapsulation Mechanism selected as an alternate candidate in NIST’s PQC standardization process, in which performance plays a significant role in the third round. This paper presents FPGA implementations of BIKE with the best area-time performance reported in literature. We optimize two key arithmetic operations, which are the sparse polynomial multiplication and the polynomial inversion. Our sparse multiplier achieves time-constancy for sparse polynomials of indefinite Hamming weight used in BIKE’s encapsulation. The polynomial inversion is based on the extended Euclidean algorithm, which is unprecedented in current BIKE implementations. Our optimized design results in a 5.5 times faster key generation compared to previous implementations based on Fermat’s little theorem.Besides the arithmetic optimizations, we present a united hardware design of BIKE with shared resources and shared sub-modules among KEM functionalities. On Xilinx Artix-7 FPGAs, our light-weight implementation consumes only 3 777 slices and performs a key generation, encapsulation, and decapsulation in 3 797 μs, 443 μs, and 6 896 μs, respectively. Our high-speed design requires 7 332 slices and performs the three KEM operations in 1 672 μs, 132 μs, and 1 892 μs, respectively.

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

Conceptual design and integration of a propulsion system for a supersonic transport aircraft

Despite 50 years of technological advancement since the inception of Concorde, research on supersonic passenger aircraft has only recently resulted in design and flight test of several small 12 to 55-passenger business jets with supersonic cruises between Mach 1.2 and 2.2. Analytical research designs of larger 300-passenger aircraft have been conducted only to speeds of Mach 2.0 and 2.2, mainly avoiding moving beyond turbojet propulsion. This research extends on an earlier multifactor regression sizing study to determine in greater design detail whether the configuration of a 200-passenger Mach 3.0 aircraft is feasible using extant technology. This research article is the second part of two and covers a suitable and cost-effective propulsion system for the executive supersonic passenger aircraft. Through this high-speed design, the research examines modern propulsion technology and the performance advancements it affords through higher efficiencies, higher metallurgical thermal limits, variable cycle engines and variable stator technology. The analysis was conducted on several potential propulsion systems using GasTurb software to obtain engine performance data. The performance results led to a combined cycle turbofan–ramjet engine as being the engine that could yield the most extensive range for the aircraft. Further investigation is needed on aircraft noise, engine emissions, the accuracy of the thrust-critical lift-to-drag ratios and the aeroelastic effects that can be closely coupled to noise and performance.

A Novel Efficient CNFET-Based Inexact Full Adder Design for Image Processing Applications

Employing inexact arithmetic circuits in error-resilient applications results in reduction of hardware-level metrics such as power consumption, delay and occupied area. These criteria are very important in portable applications because they are battery limited. Full Adder cell is as a building block of many arithmetic circuits. Therefore, it can influence the performance of the entire digital system. This paper presents a novel low-power and high-speed design of one-bit inexact full adder cell based on 32-nm (CNFET) technology for error resilient applications. This design technique can be utilized in various applications particularly in image processing. The presented design employs capacitive threshold logic (CTL) approach which significantly reduces the number of transistors. The peak signal-to-noise ratio (PSNR) is considered to evaluate accuracy of circuits at application level. Then extensive simulations regarding various power supplies, temperatures and loads at transistor level are performed to measure power consumption and propagation delay criteria. Moreover, some new metrics are introduced to trade-off between application and hardware level parameters. Comprehensive simulations demonstrate the supremacy of the proposed cell than others.

Limited Angle Electrical Resistance Tomography in Wastewater Monitoring

Electrical resistance tomography (ERT) has been investigated in monitoring conductive flows due to its high speed, non-intrusive and no radiation hazard advantages. Recently, we have developed an ERT system for the novel application of smart wastewater metering. The dedicated low cost and high-speed design of the reported ERT device allows for imaging pipes with different flow constituents and monitoring the sewer networks. This work extends the capability of such a system to work with partially filled lateral pipes where the incomplete data issue arises due to the electrodes losing contact with the conductive medium. Although the ERT for such a limited region has been developed for many years, there is no study on imaging content within these limited regions. For wastewater monitoring, this means imaging the wastewater and solid inclusions at the same time. This paper has presented a modified ERT system that has the capacity to image inclusions within the conductive region using limited data. We have adjusted the ERT hardware to register the information of the non-contact electrodes and hence the valid measurements. A limited region image reconstruction method based on Jacobian reformulation is applied to gain robustness when it comes to inclusion recovery in limited data ERT. Both simulation and experimental results have demonstrated an enhanced performance brought by the limited region method in comparison to the global reconstruction.

Design of a Voltage to Time Converter with High Conversion Gain for Reliable and Secure Autonomous Vehicles

Automation of vehicles requires a secure, reliable, and real-time on-chip system. These systems also require very high-speed and compact on-chip analog to digital converters (ADC). The conventional ADC cannot fulfill this requirement. In this paper, we proposed a Darlington pair- and source biasing-based high speed, secure, and reliable voltage to time converter (VTC). It is a compact, high-speed design and gives high conversion gain. The source biasing also helps to increase the input voltage range. The conversion gain of the proposed circuit is 101.43ns/v, which is 52 times greater than the gain achieved by state-of-the-art design. It also shows less effect of process variation and bias temperature instability.