Memory reduction by intermediate result value encoding for content-based classification

2004 ◽  
Vol 40 (17) ◽  
pp. 1041
Author(s):  
H.-S. Oh ◽  
C.-M. Kyung

e-NARODROID ◽  
2015 ◽  
Vol 1 (1) ◽  
Author(s):  
Arief Budijanto

Msb-First Adder merupakan metode penjumlahan bilangan bulat yang dilakukan mulai dari bobot bit yang paling signifikan terlebih dahulu atau dari bit paling kiri menuju kekanan. Metode pemjumlahan ini mempunyai kelebihan jika proses penjumlahan dibatasi oleh waktu (deadline), karena yang dijumlahkan terlebih dahulu adalah bit yang mempunyai bobot paling signifikan. Selain itu metoda ini juga menunjukan kinerja yang lebih baik ketika digunakan untuk menjumlahkan bilangan banyak (multioperand). Dalam penelitian ini dibuat suatu arsitektur MSB-First Adder yang diaplikasikan untuk komputasi Transformasi Fourier Diskrit (TFD). Tahapan yang dilakukan dalam peneltian ini adalah desain diagram blok arsitektur MSB-First Adder dan Arsitektur TFD yang menggunakan MSBFirst Adder, kemudian memodelkan dalam bentuk VHDL Code . Tahapan yang terakhir yaitu melakukan verifikasi dan analisis dari hasil komputasi TFD yang menggunakan MSB-First adder dibandingkan dengan TFD menggunakan LSB-First Adder dan MATLAB. Hasil akhir komputasi TFD Multioperand MSB-First dengan TFD LSB-First memperlihatkan hasil yang sama. Selain itu pada komputasi TFD Multioperand MSB-First tersedianya hasil-antara (intermediate-result) pada awal proses yang mendekati hasil akhirnya. Hasil ini tidak terjadi pada komputasi prosesor DFT LSB-First. Waktu yang dibutuhkan untuk proses komputasi TFD Multioperand MSB-First adalah 158,506 µS, sedangkan TFD LSB-First adalah 55,308 µS. Agar waktu komputasi TFD Multioperand MSB-First akan mendekati sama dengan waktu komputasi TFD LSB-First, jika pada bagian output memory (RAM dan ROM) dirubah menjadi 16 saluran output (tiap saluran 16 bit) dan multiply nya disusun paralel sebanyak 16 buah.Kata kunci: MSB-First Adder, LSB-First Adder, Hasil-Antara, VHDL, TFD





Author(s):  
Nils Brunsson ◽  
Mats Jutterström

Organizing and Reorganizing Markets is an edited volume that brings organization theory to the study of markets. The differences between markets and organizations are often exaggerated. Both are organized. Organizing exists in addition to other processes and phenomena that form markets: the mutual adaption among sellers and buyers as described in mainstream economics and the institutions described in institutional economics and economic sociology. Market organization can be analysed with the same type of theories used for analysing organization within formal organizations. Through the use of many empirical examples, the book demonstrates how this can be done. We argue that the way a certain market is organized can be understood as the (intermediate) result of previous organizing processes. We discuss such questions as ‘What drives market organizing and reorganizing processes? What makes various organizations intervene as market organizers? And how are the specific contents of market organization determined?’ The answers to these questions help us to analyse similarities and differences among organizing processes in formal organizations and those in markets. The arguments are illustrated by in-depth studies of many types of markets. The book is intended to open up markets as a field of study for scholars of organization. Although the chapters have different authors, they use and elaborate upon the same general theoretical framework. The book contributes to the issue of organization outside and among organizations where a fundamental concept is that of partial organization.





2015 ◽  
Vol 2015 ◽  
pp. 1-12 ◽  
Author(s):  
Jérôme Leclère ◽  
Cyril Botteron ◽  
René Jr. Landry ◽  
Pierre-André Farine

With modern global navigation satellite system (GNSS) signals, the FFT-based parallel code search acquisition must handle the frequent sign transitions due to the data or the secondary code. There is a straightforward solution to this problem, which consists in doubling the length of the FFTs, leading to a significant increase of the complexity. The authors already proposed a method to reduce the complexity without impairing the probability of detection. In particular, this led to a 50% memory reduction for an FPGA implementation. In this paper, the authors propose another approach, namely, the splitting of a large FFT into three or five smaller FFTs, providing better performances and higher flexibility. For an FPGA implementation, compared to the previously proposed approach, at the expense of a slight increase of the logic and multiplier resources, the splitting into three and five allows, respectively, a reduction of 40% and 64% of the memory, and of 25% and 37.5% of the processing time. Moreover, with the splitting into three FFTs, the algorithm is applicable for sampling frequencies up to 24.576 MHz for L5 band signals, against 21.846 MHz with the previously proposed algorithm. The algorithm is applied here to the GPS L5 and Galileo E5a, E5b, and E1 signals.



Author(s):  
V. V. HRYTSYK ◽  
K. M. BEREZSKA ◽  
O. M. BEREZSKY

We propose a method of description and modeling of complex symmetrical images, which can be used for the synthesis of ornamental patterns. Our approach allows considerable memory reduction for storing symmetrical images and considerable time reduction for their synthesis. Our algorithms for ornamental patterns synthesis suggest the design of a special purpose ornamental patterns editor which can store and synthesize symmetrical images.



2004 ◽  
Vol 74 (7) ◽  
pp. 501-511 ◽  
Author(s):  
Raymond H. Chan ◽  
Yong Chen † ◽  
K. M. Yeung ‡


2018 ◽  
Vol 29 (08) ◽  
pp. 1249-1255
Author(s):  
Kamil Salikhov

Modern DNA sequencing technologies generate prodigious volumes of sequence data consisting of short DNA fragments (reads). Storing and transferring this data is often challenging. With this motivation, several specialized compression methods have been developed. In this paper, we present an improvement of the lossless reference-free compression algorithm, suggested by Rozov et al., based on the technique of cascading Bloom filters. Through computational experiments on real data, we demonstrate that our method results in a significant associated memory reduction in practice.



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