Power efficient error correction coding for on-chip interconnection links

2020 ◽  
Vol 14 (6) ◽  
pp. 299-312
Author(s):  
Sumitra Velayudham ◽  
Sivakumar Rajagopal ◽  
Yeragudipati Venkata Ramana Rao ◽  
Seok-Bum Ko
Keyword(s):  
Error Correction ◽  
Error Correction Coding ◽  
Power Efficient ◽  
On Chip

Hamming Product Code Based Multiple Bit Error Correction Coding Scheme Using Keyboard Scan Based Decoding for on Chip Interconnects Links

2012 ◽  
Vol 241-244 ◽  
pp. 2457-2461 ◽  
Author(s):  
Murali Maheswari ◽  
Gopalakrishnan Seetharaman
Keyword(s):  
Error Correction ◽  
Error Rate ◽  
Iterative Decoding ◽  
Error Control ◽  
Low Complexity ◽  
Hardware Complexity ◽  
Error Correction Coding ◽  
Product Code ◽  
Coding Scheme ◽  
On Chip

In this paper, we present multiple bit error correction coding scheme using extended Hamming product code combined with type II HARQ and keyboard scan based error flipping to correct multiple bit errors for on chip interconnect. The keyboard scan based error flipping reduces the hardware complexity of the decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 86% of reduction in area and 23% of reduction in decoder delay with only small increase in residual flit error rate compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 66% of links power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

scholarly journals Lightweight hamming product code based multiple bit error correction coding scheme using shared resources for on chip interconnects

2020 ◽  
Vol 9 (5) ◽  
pp. 1979-1989
Author(s):  
Asaad Kadhum Chlaab ◽  
Wameedh Nazar Flayyih ◽  
Fakhrul Zaman Rokhani
Keyword(s):  
Power Consumption ◽  
Error Correction ◽  
Error Rate ◽  
Iterative Decoding ◽  
Total Power ◽  
Shared Resources ◽  
Error Correction Coding ◽  
Product Code ◽  
Coding Scheme ◽  
On Chip

In this paper, we present multiple bit error correction coding scheme based on extended Hamming product code combined with type II HARQ using shared resources for on chip interconnect. The shared resources reduce the hardware complexity of the encoder and decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 20% and 28% reduction in area and power consumption respectively, with only small increase in decoder delay compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 58% of total power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

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