Erratum: Effect of adding DC‐offset estimation integrators in there‐phase enhanced phase‐locked loop on dynamic performance and alternative scheme

2015 ◽  
Vol 8 (6) ◽  
pp. 1081-1081
2021 ◽  
Vol 2021 ◽  
pp. 1-9
Author(s):  
Fehmi Sevilmiş ◽  
Hulusi Karaca

Recently, several approaches with the ability to reject the DC-offset in phase locked loop (PLL) methods have been developed. These approaches include different filtering structures which can be classified into two categories: prefiltering before the PLL input and in-loop filtering in the PLL control loop. As highlighted in the literature, the DC-offset rejection methods based on in-loop filtering have received less attention due to their slow dynamic performance. Therefore, this paper proposes an alternative DC-offset rejection technique as in-loop filtering of the PLL. The effectiveness of the proposed PLL is confirmed by simulation and experimental results.


Author(s):  
Issam A. Smadi ◽  
Bayan H. Bany Fawaz

AbstractFast and accurate monitoring of the phase, amplitude, and frequency of the grid voltage is essential for single-phase grid-connected converters. The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closed-loop stability of the grid-connected converters. In this paper, a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation (ADSC) in a second-order generalized integrator (SOGI) phase-locked loop (PLL). A frequency-fixed SOGI-based PLL (FFSOGI-PLL) is adopted to ensure better stability and to reduce the complexity compared with other SOGI-based PLLs. A small-signal model of the proposed PLL is derived for the systematic design of proportional-integral (PI) controller gains. The effects of frequency variation and ADSC on the proposed PLL are considered, and correction methods are adopted to accurately estimate grid information. The simulation results are presented, along with comparisons to other single-phase PLLs in terms of settling time, peak frequency, and phase error to validate the proposed PLL. The dynamic performance of the proposed PLL is also experimentally validated. Overall, the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices, offering an improved solution for precise grid synchronization in single-phase applications.


Energies ◽  
2018 ◽  
Vol 11 (9) ◽  
pp. 2472 ◽  
Author(s):  
Yunlu Li ◽  
Junyou Yang ◽  
Haixin Wang ◽  
Weichun Ge ◽  
Yiming Ma

In renewable energy generation applications, phase locked loop (PLL) is one of the most popular grid synchronization technique. The main objective of PLL is to rapidly and precisely extract phase and frequency especially when the grid voltage is under non-ideal conditions. This motivates the recent development of moving average filters (MAFs) based PLL in a quasi-type-1 system (i.e., QT1-PLL). Despite its success in certain applications, the transient response is still unsatisfactory, mainly due to the fact that the time delay caused by MAFs is still large. This has significantly limited the utilization of QT1-PLL, according to common grid codes such as German and Spanish grid codes. This challenge has been tackled in this paper. The basic idea is to develop a new hybrid filtering stage, consisting of adaptive notch filters (ANFs) and MAFs, arranged at the inner loop of QT1-PLL. Such an idea can greatly improve the transient response of QT1-PLL, owing to the fact that ANFs are utilized to remove the fundamental frequency negative voltage sequence (FFNS) component while other dominant harmonics can be removed by MAFs with a small time delay. By applying the proposed technique, the settling time is reduced to less than one cycle of grid frequency without any degradation in filtering capability. Moreover, the proposed PLL can be easily expanded to handle dc offset rejection. The effectiveness is validated by comprehensive experiments.


1977 ◽  
Vol 10 (1) ◽  
pp. 27-34
Author(s):  
W. F. Ray

In this paper a frequency-to-voltage converter is proposed for use as a speed transducer over a 100:1 range. It aims to keep to a minimum the number of pulses per revolution of the opto-electrical transducer required whilst also minimising the output voltage ripple content and giving an adequate speed of response. It operates on the basis of a phase-locked loop giving a modulation of constant mark-space ratio over the frequency range. Mathematical models of the converter are derived to analyse and predict its dynamic performance and the behaviour of a prototype practical circuit is examined.


2014 ◽  
Vol 7 (9) ◽  
pp. 2288-2299 ◽  
Author(s):  
Slobodan Lubura ◽  
Milomir Šoja ◽  
Srd‐an Lale ◽  
Marko Ikić

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