High performance perpendicular magnetic tunnel junction with Co/Ir interfacial anisotropy for embedded and standalone STT-MRAM applications

2018 ◽  
Vol 112 (9) ◽  
pp. 092402 ◽  
Author(s):  
Yiming Huai ◽  
Huadong Gan ◽  
Zihui Wang ◽  
Pengfa Xu ◽  
Xiaojie Hao ◽  
...  
Sensors ◽  
2019 ◽  
Vol 19 (20) ◽  
pp. 4475 ◽  
Author(s):  
Jiafei Hu ◽  
Minhui Ji ◽  
Weicheng Qiu ◽  
Long Pan ◽  
Peisen Li ◽  
...  

To improve the sensitivity of the magnetic tunnel junction(MTJ)sensor, a novel architecture for a double-gap magnetic flux concentrator (MFC) was studied theoretically and experimentally in this paper. The three-dimensional finite element model of magnetic flux was established to optimize the magnetic field amplification factor, with different gaps. The simulation results indicate that the sensitivity of an MTJ sensor with a double-gap MFC can be significantly better than that of a sensor with a traditional single-gap MFC, due to the fact that the magnetic magnification sharply increases with the decrease in effective gap width. Besides this, the half-bridge MTJ sensors with the double-gap MFC were fabricated using photolithography, ion milling, evaporation, and electroplating processes. Experimental results show that the sensitivity of the MTJ sensor increased by ten times compared to the sensor without the double-gap MFC, which underlines the theoretical predictions. Furthermore, there is no significant increase in the sensor noise. The work in this paper contributes to the development of high-performance MTJ sensors.


SPIN ◽  
2013 ◽  
Vol 03 (04) ◽  
pp. 1340014 ◽  
Author(s):  
TAKAHIRO HANYU

This paper presents an architecture-level approach, called nonvolatile logic-in-memory (NV-LIM) architecture, to solving performance-wall and power-wall problems in the present CMOS-only-based logic-LSI (Large-Scaled Integration) processors. The use of magnetic tunnel junction devices combined with a CMOS-gate style makes it possible to achieve a high-performance and ultra-low-power logic LSI. Some concrete examples using the proposed method allow you to achieve the desired performance improvement compared to a corresponding CMOS-only-based realization.


2021 ◽  
pp. 1-1
Author(s):  
E. Monteblanco ◽  
A. Solignac ◽  
C. Chopin ◽  
J. Moulin ◽  
P. Belliot ◽  
...  

2021 ◽  
Vol 4 (6) ◽  
pp. 392-398 ◽  
Author(s):  
E. Raymenants ◽  
O. Bultynck ◽  
D. Wan ◽  
T. Devolder ◽  
K. Garello ◽  
...  

2020 ◽  
Vol 2 (12) ◽  
pp. 2070120
Author(s):  
Jeongmin Hong ◽  
Xin Li ◽  
Nuo Xu ◽  
Hong Chen ◽  
Stefano Cabrini ◽  
...  

2021 ◽  
Vol 118 (11) ◽  
pp. 112401
Author(s):  
Mahshid Alamdar ◽  
Thomas Leonard ◽  
Can Cui ◽  
Bishweshwor P. Rimal ◽  
Lin Xue ◽  
...  

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