2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)
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Thermal stability and scalability of Zr-aluminate-based high-k gate stacks

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) ◽

10.1109/vlsit.2002.1015448 ◽

2003 ◽

Cited By ~ 4

Author(s):

P.J. Chen ◽

E. Cartier ◽

R.J. Carter ◽

T. Kauerauf ◽

C. Zhao ◽

...

Keyword(s):

Thermal Stability ◽

Gate Stacks ◽

High K

A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm CMOS generation

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) ◽

10.1109/vlsit.2002.1015377 ◽

2003 ◽

Cited By ~ 5

Author(s):

N. Oda ◽

S. Ito ◽

T. Takewaki ◽

H. Kunishima ◽

N. Hironaga ◽

...

Keyword(s):

Interconnect Technology

110 GHz cutoff frequency of ultra-thin gate oxide p-MOSFETs on [110] surface-oriented Si substrate

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) ◽

10.1109/vlsit.2002.1015431 ◽

2003 ◽

Cited By ~ 13

Author(s):

H.S. Momose ◽

T. Ohguro ◽

K. Kojima ◽

S. Nakamura ◽

Y. Toyoshima

Keyword(s):

Cutoff Frequency ◽

Gate Oxide ◽

Si Substrate ◽

Thin Gate Oxide

A porous Si based novel isolation technology for mixed-signal integrated circuits

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) ◽

10.1109/vlsit.2002.1015433 ◽

2003 ◽

Cited By ~ 1

Author(s):

Han-Su Kim ◽

Kyuchul Chong ◽

Ya-Hong Xie ◽

M. Devincentis ◽

T. Itoh ◽

...

Keyword(s):

Integrated Circuits ◽

Porous Si ◽

Mixed Signal

High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) ◽

10.1109/vlsit.2002.1015436 ◽

2003 ◽

Author(s):

I. Kudo ◽

S. Miyake ◽

T. Syo ◽

S. Maruyama ◽

Y. Yama ◽

...

Keyword(s):

High Performance ◽

Cmos Technology ◽

Low K

MOSFET scalability limits and "new frontier" devices

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) ◽

10.1109/vlsit.2002.1015365 ◽

2003 ◽

Cited By ~ 8

Author(s):

D.A. Antoniadis

Keyword(s):

New Frontier

Low standby power CMOS with HfO/sub 2/ gate oxide for 100-nm generation

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) ◽

10.1109/vlsit.2002.1015375 ◽

2003 ◽

Cited By ~ 3

Author(s):

S. Pidin ◽

Y. Morisaki ◽

Y. Sugita ◽

T. Aoyama ◽

K. Irino ◽

...

Keyword(s):

Gate Oxide ◽

Standby Power

Highly manufacturable 32 Mb ULP-SRAM technology by using dual gate process for 1.5 V Vcc operation

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) ◽

10.1109/vlsit.2002.1015416 ◽

2003 ◽

Cited By ~ 1

Author(s):

D.H. Kim ◽

S.J. Kim ◽

B.J. Hwang ◽

S.H. Seo ◽

J.H. Choi ◽

...

Keyword(s):

Dual Gate

>100< channel strained-SiGe p-MOSFET with enhanced hole mobility and lower parasitic resistance

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) ◽

10.1109/vlsit.2002.1015403 ◽

2003 ◽

Cited By ~ 2

Author(s):

M. Shima ◽

T. Ueno ◽

T. Kumise ◽

H. Shido ◽

Y. Sakuma ◽

...

Keyword(s):

Hole Mobility ◽

Parasitic Resistance ◽

Strained Sige

Highly manufacturable sub-100 nm DRAM integrated with full functionality

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) ◽

10.1109/vlsit.2002.1015385 ◽

2003 ◽

Cited By ~ 1

Author(s):

S. Choi ◽

B.Y. Nam ◽

J.-H. Ku ◽

D.C. Kim ◽

S.H. Lee ◽

...

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Thermal stability and scalability of Zr-aluminate-based high-k gate stacks

A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm CMOS generation

110 GHz cutoff frequency of ultra-thin gate oxide p-MOSFETs on [110] surface-oriented Si substrate

A porous Si based novel isolation technology for mixed-signal integrated circuits

High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors

MOSFET scalability limits and "new frontier" devices

Low standby power CMOS with HfO/sub 2/ gate oxide for 100-nm generation

Highly manufacturable 32 Mb ULP-SRAM technology by using dual gate process for 1.5 V Vcc operation

>100< channel strained-SiGe p-MOSFET with enhanced hole mobility and lower parasitic resistance

Highly manufacturable sub-100 nm DRAM integrated with full functionality

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)
Latest Publications