A novel design of ultra-broadband, high-gain and high-linearity variable gain distributed amplifier in 0.13 μm CMOS technology

2016 ◽  
Vol 103 (12) ◽  
pp. 2075-2089
Author(s):  
Zainab Baharvand ◽  
Ahmad Hakimi ◽  
Esmat Rashedi
Keyword(s):  
Cmos Technology ◽  
High Gain ◽  
Variable Gain ◽  
Distributed Amplifier ◽  
High Linearity ◽  
Novel Design

10 Gb/s Burst-Mode Transimpedance Preamplifier in 0.13µm CMOS Technology

2012 ◽  
Vol 241-244 ◽  
pp. 2215-2220
Author(s):  
Gao Wei Gu ◽  
En Zhu
Keyword(s):  
Gain Control ◽  
Cmos Technology ◽  
Fast Response ◽  
High Gain ◽  
Settling Time ◽  
Output Buffer ◽  
Peak Detector ◽  
Burst Mode ◽  
Variable Gain ◽  
Response Peak

A 10Gbit/s burst-mode transimpedance preamplifier is described. Regulated cascade (RGC) TIA core with variable gain, fast response peak detector, single-to-differential and output buffer are included, providing auto-gain-control and threshold extraction functions. The burst-mode preamplifier is implemented by 0.13µm CMOS technology, presents a high gain of 67.9dB with a 3-dB bandwidth of 6.92GHz and a low gain of 57.4dB with a 3-dB bandwidth of 8.60GHz with a settling time less than 20ns.

Analysis and Design of High Gain-Bandwidth CMOS Distributed Amplifier Utilizing a Cascaded Pseudo Differential Distributed Amplifier

2020 ◽  
pp. 2150005
Author(s):  
Majid Babaeinik ◽  
Massoud Dousti ◽  
Mohammad Bagher Tavakoli
Keyword(s):  
Noise Figure ◽  
Cell Structure ◽  
Cmos Technology ◽  
High Gain ◽  
Rf Cmos ◽  
Chip Area ◽  
Distributed Amplifiers ◽  
Analysis And Design ◽  
Distributed Amplifier ◽  
Three Stages

Distributed amplifiers (DAs) are one of the most important and common wideband amplifiers that can use various arrangements in their gain cell structure. One of the gain cells that can be effective in increasing the bandwidth of a distributed amplifier is the pseudo-differential amplifier (PDA). Although pseudo-differential distributed amplifiers (PDDAs) have a wide bandwidth and amplify DC, they have a small voltage gain. In this paper, various circuits with the same power and chip area are proposed to improve the performance of PDDAs. For evaluating and comparing the performance of the proposed circuits, they are implemented in 0.18[Formula: see text][Formula: see text]m RF-CMOS technology. The simulation results reveal that two cascaded PDDAs with three stages have a better performance than three cascaded PDDAs with two stages; in two cascaded PDDAs with three stages, a gain of 9[Formula: see text]dB can be achieved for a bandwidth of 50[Formula: see text]GHz in 0.18[Formula: see text][Formula: see text]m RF-CMOS technology. In this amplifier, parameters S[Formula: see text], S[Formula: see text] and S[Formula: see text] are [Formula: see text]12, [Formula: see text]10 and [Formula: see text]18 dB, respectively; noise figure is 4.3–5.8[Formula: see text]dB, and [Formula: see text] is +4[Formula: see text]dBm. This amplifier consumes 220[Formula: see text]mW power and has a chip area of 0.58[Formula: see text]mm2.

A band selected 3.1-30.1 GHz distributed amplifier in 0.18-μm CMOS technology

2011 ◽  
Vol 53 (8) ◽  
pp. 1850-1853
Author(s):  
Wu-Shiung Feng ◽  
Chien-Cheng Wei ◽  
Hui-Chen Hsu ◽  
Chia-Hsun Chen ◽  
Prasenjit Chatterjee ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Distributed Amplifier

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

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