Research on ultra-smooth machining technique for monocrystalline silicon substrate

2020 ◽  
Vol 67 (14) ◽  
pp. 1227-1232
Author(s):  
Zhe Wang ◽  
Lingqi Wu ◽  
Aihuan Dun ◽  
Yuanyuan Fang ◽  
Li Song ◽  
...  
2011 ◽  
Vol 56 (1-4) ◽  
pp. 223-231 ◽  
Author(s):  
Wen-Tse Hsiao ◽  
Shih-Feng Tseng ◽  
Kuo-Cheng Huang ◽  
Yan-Hsin Wang ◽  
Ming-Fei Chen

2000 ◽  
Vol 624 ◽  
Author(s):  
S.Y. Tan ◽  
R.J. Gambino ◽  
R. Goswami ◽  
S. Sampath ◽  
H. Herman

ABSTRACTPolycrystalline silicon deposits were formed on a monocrystalline silicon substrate by thermal spraying. The resulting structure exhibits a device characteristic. Pressure-induced transformations of silicon, namely, Si-III (BC-8) and Si-IX are identified by X-ray diffraction in a Si-I matrix on deposits formed by vacuum plasma spray. The presence of the Si-III and Si-IX indicates that the pressure-quenched silicon deposit is highly conductive, as determined by four-point van der Pauw resistivity measurement. Hall mobility measurements, combined with photoconductivity results, indicate that the highly conductive silicon deposit displays the same range of mobility as a polycrystalline deposit containing only Si-I. The silicon deposit, with or without metastable phases, displays the same photoconductivity properties. The silicon deposit on a monocrystalline silicon substrate exhibits rectifying I–Vcharacteristics, possibly caused by band bending of trapping states associated with impurities segregating at the polycrystalline deposit/monocrystalline substrate interface


2019 ◽  
Vol 522 ◽  
pp. 86-91 ◽  
Author(s):  
Meng Chen ◽  
Nuofu Chen ◽  
Quanli Tao ◽  
Zhenwen Chang ◽  
Jikun Chen

2014 ◽  
Vol E97.C (7) ◽  
pp. 677-682
Author(s):  
Sung YUN WOO ◽  
Young JUN YOON ◽  
Jae HWA SEO ◽  
Gwan MIN YOO ◽  
Seongjae CHO ◽  
...  

2014 ◽  
Vol 2 (1) ◽  
pp. 20-23
Author(s):  
Jaskiran Kaur ◽  
◽  
Surinder Singh ◽  

Author(s):  
J.G. van Hassel ◽  
Xiao-Mei Zhang

Abstract Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.


Author(s):  
Younan Hua ◽  
Bingsheng Khoo ◽  
Henry Leong ◽  
Yixin Chen ◽  
Eason Chan ◽  
...  

Abstract In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.


2016 ◽  
Vol 12 (5) ◽  
pp. 464-471 ◽  
Author(s):  
Amina Omar ◽  
El-Sayed M. El-Sayed ◽  
Mona S. Talaat ◽  
Medhat Ibrahim

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