Low voltage stress-induced leakage current and traps in ultrathin oxide (1.2–2.5 nm) after constant voltage stresses

2007 ◽  
Vol 22 (10) ◽  
pp. 1165-1173 ◽  
Author(s):  
C Petit ◽  
D Zander
2010 ◽  
Vol 1252 ◽  
Author(s):  
Sahar Sahhaf ◽  
Robin Degraeve ◽  
Mohammed Zahid ◽  
Guido Groeseneken

AbstractIn this work, the effect of elevated temperature on the generated defects with constant voltage stress (CVS) in SiO2 and SiO2/HfSiO stacks is investigated. Applying Trap Spectroscopy by Charge Injection and Sensing (TSCIS) to 6.5 nm SiO2 layers, different kinds of generated traps are profiled at low and high temperature. Also the Stress-Induced Leakage Current (SILC) spectrum of high-k dielectric stack is different at elevated temperature indicating that degradation and breakdown at high temperature is not equivalent to that at low temperature and therefore, extrapolation of data from high to low T or vice versa is challenging.


2005 ◽  
Vol 20 (8) ◽  
pp. 668-672 ◽  
Author(s):  
Robert O'Connor ◽  
Stephen McDonnell ◽  
Greg Hughes ◽  
Robin Degraeve ◽  
Thomas Kauerauf

2006 ◽  
Vol 504 (1-2) ◽  
pp. 307-311
Author(s):  
Y.J. Yu ◽  
Q. Guo ◽  
X. Zeng ◽  
H. Li ◽  
S.H. Liu ◽  
...  

2010 ◽  
Vol 171 (1-3) ◽  
pp. 159-161 ◽  
Author(s):  
Tingting Tan ◽  
Zhengtang Liu ◽  
Hao Tian ◽  
Wenting Liu

2008 ◽  
Vol 104 (5) ◽  
pp. 053718 ◽  
Author(s):  
Paul E. Nicollian ◽  
Anand T. Krishnan ◽  
Vijay K. Reddy

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