Ultrathin nitride/oxide (N/O) gate dielectrics for p/sup +/-polysilicon gated PMOSFETs prepared by a combined remote plasma enhanced CVD/thermal oxidation process

1998 ◽  
Vol 19 (10) ◽  
pp. 367-369 ◽  
Author(s):  
Y. Wu ◽  
G. Lucovsky
Refractories ◽  
1992 ◽  
Vol 33 (1-2) ◽  
pp. 14-18
Author(s):  
Yu. A. Pirogov ◽  
P. Ya. Pustovar ◽  
I. A. Kutuzyan ◽  
Yu. F. Boiko

2004 ◽  
Vol 457-460 ◽  
pp. 1357-1360 ◽  
Author(s):  
Antonella Poggi ◽  
Roberta Nipoti ◽  
Sandro Solmi ◽  
M. Bersani ◽  
L. Vanzetti

2000 ◽  
Vol 623 ◽  
Author(s):  
J. C. Ferrer ◽  
Z. Liliental-Weber ◽  
H. Reese ◽  
Y.J. Chiu ◽  
E. Hu

AbstractThe lateral thermal oxidation process of Al0.98Ga0.02As layers has been studied by transmission electron microscopy. Growing a low-temperature GaAs layer below the Al0.98Ga0.02As has been shown to result in better quality of the oxide/GaAs interfaces compared to reference samples. While the later have As precipitation above and below the oxide layer and roughness and voids at the oxide/GaAs interface, the structures with low-temperature have less As precipitation and develop interfaces without voids. These results are explained in terms of the diffusion of the As toward the low temperature layer. The effect of the addition of a Si02 cap layer is also discussed.


1996 ◽  
Vol 143 (1) ◽  
pp. 244-251 ◽  
Author(s):  
S. Nakashima ◽  
T. Katayama ◽  
Y. Miyamura ◽  
A. Matsuzaki ◽  
M. Kataoka ◽  
...  

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