An all-digital built-in self-test for high-speed phase-locked loops

2001 ◽  
Vol 48 (2) ◽  
pp. 141-150 ◽  
Author(s):  
Seongwon Kim ◽  
M. Soma
Keyword(s):  
High Speed ◽  
Phase Locked Loops ◽  
Self Test ◽  
Built In Self Test

Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

2021 ◽  
Vol 26 (3) ◽  
pp. 1-18
Author(s):  
Mehmet Ince ◽  
Ender Yilmaz ◽  
Wei Fu ◽  
Joonsung Park ◽  
Krishnaswamy Nagaraj ◽  
...  
Keyword(s):  
Phase Locked Loops ◽  
Test And Evaluation ◽  
Self Test ◽  
Built In Self Test

Design for Testability of High-Speed Advance Multipliers

2020 ◽  
pp. 175-190
Author(s):  
Suman Lata Tripathi
Keyword(s):  
High Speed ◽  
High Performance ◽  
Design For Testability ◽  
Online Testing ◽  
Efficient Design ◽  
Self Test ◽  
Built In Self Test ◽  
Work Done ◽  
Testing Work ◽  
Circuit Under Test

An efficient design for testability (DFT) has been a major thrust of area for today's VLSI engineers. A poorly designed DFT would result in losses for manufacturers with a considerable rework for the designers. BIST (built-in self-test), one of the promising DFT techniques, is rapidly modifying with the advances in technology as the device shrinks. The increasing complexities of the hardware have shifted the trend to include BISTs in high performance circuitry for offline as well as online testing. Work done here involves testing a circuit under test (CUT) with built in response analyser and vector generator with a monitor to control all the activities.

A Half-Rate Built-In Self-Test for High-Speed Serial Interface using a PRBS Generator and Checker

2019 ◽  
Author(s):  
Ram Ratnaker Reddy Bodha ◽  
Sahar Sarafi ◽  
Ajinkya Kale ◽  
Michael Koberle ◽  
Johannes Sturm
Keyword(s):  
High Speed ◽  
Serial Interface ◽  
Self Test ◽  
Built In Self Test

Built-In Self-Test for Phase-Locked Loops

2005 ◽  
Vol 54 (3) ◽  
pp. 996-1002 ◽  
Author(s):  
C.-L. Hsu ◽  
Y. Lai ◽  
S.-W. Wang
Keyword(s):  
Phase Locked Loops ◽  
Self Test ◽  
Built In Self Test
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