Power efficient MPEG-4 decoder architecture featuring low-complexity error resilience

Author(s):  
H.I. Byun ◽  
M.Y. Jeon ◽  
J.Y. Seo ◽  
K.W. Lee ◽  
S.H. Lee ◽  
...  
Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 516
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.


Optik ◽  
2021 ◽  
pp. 168245
Author(s):  
Samy S. Soliman ◽  
Mohamed Shehata ◽  
Hassan Mostafa

Author(s):  
Houssem Sifaou ◽  
Abla Kammoun ◽  
Luca Sanguinetti ◽  
Merouane Debbah ◽  
Mohamed-Slim Alouini

Author(s):  
Kirti Samir Vaidya ◽  
C. G. Dethe ◽  
S. G. Akojwar

A solution for existing and upcoming wireless communication standards is a software-defined radio (SDR) that extracts the desired radio channel. Channelizer is supposed to be the computationally complex part of SDR. In multi-standard wireless communication, the Software Radio Channelizer is often used to extract individual channels from a wideband input signal. Despite the effective channelizer design that reduces computing complexity, delay and power consumption remain a problem. Thus, to promote the effectiveness of the channelizer, we have provided the Non-Maximally Coefficient Symmetry Multirate Filter Bank. In this paper, to improve the hardware efficiency and functionality of the proposed schemes, we propose a polyphase decomposition and coefficient symmetry incorporated into the Non-Maximally Coefficient Symmetry Multirate Filter Bank. For sharp wideband channelizers, the proposed methods are suitable. Furthermore, polyphase decomposition filter and coefficient symmetry is incorporated into the Non-Maximally Coefficient Symmetry Multirate Filter Bank to improve the hardware efficiency, power efficient, flexibility, reduce hardware size and functionality of the proposed methods. To prove the complexity enhancement of the proposed system, the design to be the communication standard for complexity comparison.


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