Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations
1990 ◽
Vol 33
(10)
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pp. 1319-1326
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2016 ◽
Vol 859
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pp. 188-193
1997 ◽
Vol 211
(3)
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pp. 233-237
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1995 ◽
Vol 48
(1)
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pp. 63-71
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2001 ◽
Vol 20
(3)
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pp. 458-474
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