In this paper, we present an algorithm for circuit partitioning with complex resource
constraints in large FPGAs. Traditional partitioning methods estimate the capacity of
an FPGA device by counting the number of logic blocks, however this is not accurate
with the increasing diverse resource types in the new FPGA architectures. We first
propose a network flow based method to optimally check whether a circuit or a subcircuit
is feasible for a set of available heterogeneous resources. Then the feasibility
checking procedure is integrated in the FM-based algorithm for circuit partitioning.
Incremental flow technique is employed for efficient implementation. Experimental
results on the MCNC benchmark circuits show that our partitioning algorithm not only
yields good results, but also is efficient. Our algorithm for partitioning with complex
resource constraints is applicable for both multiple FPGA designs (e.g., logic emulation
systems) and partitioning-based placement algorithms for a single large hierarchical
FPGA (e.g., Actel's ES6500 FPGA family).
FPGA Partitioning with Complex Resource Constraints
