There are certain difficulties in the development of a broadband generator of quadrature signals (QSG) on a SiGe BiCMOS technology. The problem of linearity and broadband matching is the most difficult to solve. When designing QSG in a wide frequency band, there is a problem of forming a quadrature signal using traditional solutions using a polyphase filter or a digital D-trigger. The use of only one method for forming a quadrature signal is impossible due to the limiting features of the electronic component base of SiGe BiCMS technology. To solve this problem, we propose a structure that allows us to develop a broadband quadrature signal generator with an operating frequency range from 10 MHz to 6 GHz, using the method of dividing the operating frequency band. At frequencies from 1 to 6 GHz, the quadrature signal is generated using a polyphase filter, and at frequencies less than 1 GHz using a frequency divider. Using this method, the following characteristics of the FCS have been achieved: the difference in the amplitudes of quadrature signals is less than 0.3 dB; the VSWR is less than 1.6 over the entire frequency range; the transmission coefficient is not less than -2 dB at a 0 dBm heterodyne power; at a frequency of 6 GHz P1dB of at least 3 dBm. The experimental results are in good agreement with the simulation data.
An Efficient FPGA Implementation of a Quadrature Signal-Generation Subsystem in SRF PLLs in Single-Phase PFCs