A 1.8-V frequency synthesizer for WCDMA in 0.18-μm CMOS process

2003 ◽  
Author(s):  
Young-Mi Lee ◽  
Ju-Sang Lee ◽  
Ri-A Ju ◽  
Kang-Wook Kim ◽  
Sang-Dae Yu
Keyword(s):  
Frequency Synthesizer ◽  
Cmos Process

scholarly journals A Reconfigurable Radio-Frequency Converter IC in 0.18 µm CMOS

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1146
Author(s):  
Carlos Sánchez-Azqueta ◽  
Erick Guerrero ◽  
Cecilia Gimeno ◽  
Santiago Celma
Keyword(s):  
Wavelength Division Multiplexing ◽  
Frequency Synthesizer ◽  
Frequency Converter ◽  
Impedance Matching ◽  
Cmos Process ◽  
Wavelength Division ◽  
Triple Play ◽  
Band Pass ◽  
Reconfigurable Radio ◽  
Lc Tank

This work presents a reconfigurable RF converter for DVB-T television applications using triple-play over GPON. The system takes the DVB-T input, a wavelength division multiplexing (WDM) signal with spectral inversion in the range from 47 M Hz –1000 M Hz , up-converts its frequency to the band-pass of a highly selective surface-acoustic wave (SAW) filter centered at 1 . 3 G Hz , and then down-converts it so that it is compatible with the antenna input of conventional television sets. The designed RF converter incorporates two pairs of frequency synthesizer and mixer, based, respectively, on an integer-N phase-locked loop (PLL) with two LC-tank VCOs with 128 coarse tuning bands in the range from 1.35 G Hz –2.7 G Hz , and a double-balanced Gilbert cell, modified for better impedance matching and improved linearity. It is fed with regulated supplies compensated in temperature and programmed by an I 2 C interface operating on five 16-bit registers. This work presents the experimental characterization of the whole system plus selected cells for stand-alone testing, which have been fabricated in a 0 . 18 m CMOS process.

A design of the frequency synthesizer for UWB application in 0.13 μm RF CMOS process

2007 ◽  
Author(s):  
Jin-Kyung Kim ◽  
Sung-Kyu Jung ◽  
Ji-Hoon Jung ◽  
Kang-Yoon Lee ◽  
Chul Nam ◽  
...  
Keyword(s):  
Frequency Synthesizer ◽  
Cmos Process ◽  
Rf Cmos

A 2-V 2.3/4.6-GHz Dual-Band Frequency Synthesizer in 0.35->tex<$muhboxm $>/tex<Digital CMOS Process

2004 ◽  
Vol 39 (1) ◽  
pp. 234-237 ◽  
Author(s):  
W.-Z. Chen ◽  
J.-X. Chang ◽  
Y.-J. Hong ◽  
M.-T. Wong ◽  
C.-L. Kuo
Keyword(s):  
Frequency Synthesizer ◽  
Dual Band ◽  
Cmos Process ◽  
Digital Cmos ◽  
Band Frequency

DESIGN OF A FULLY INTEGRATED 2.4 GHz FREQUENCY PLL SYNTHESIZER FOR ZigBee TRANSCEIVER APPLICATION

2014 ◽  
Vol 23 (10) ◽  
pp. 1450137 ◽  
Author(s):  
DI LI ◽  
YINTANG YANG ◽  
DUAN ZHOU ◽  
YANI LI ◽  
XIAOPENG WU
Keyword(s):  
Frequency Synthesizer ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Frequency Resolution ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Amplitude Control ◽  
Fully Integrated ◽  
Automatic Amplitude Control ◽  
Metal Insulator Metal

A 2.4-GHz fully integrated frequency synthesizer is presented in this paper for Low-IF ZigBee (IEEE802.15.4) transceiver applications. The frequency synthesizer meets the system requirement of 2.4–2.4835 GHz frequency range with a frequency resolution of 5 MHz. The automatic-amplitude control (AAC) technique is employed for the voltage-controlled oscillator (VCO) which helps to optimize the output amplitude of the VCO over voltage, process and temperature variations. The chip has been fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process using a single poly layer, four metal layers and metal–insulator–metal (MIM) capacitors. The synthesized has a current dissipation of 4.7 mA from a 1.8 V power supply and occupies an area of 1 mm2 × 0.85 mm2. Measurement results show that the phase noise are -82 dBc/Hz–100 kHz offset and -109 dBc/Hz–1 MHz offset respectively.

The Delta-Sigma Modulator of Fractional-N Frequency Synthesizer for Wireless Sensors Network Applications

2014 ◽  
Vol 609-610 ◽  
pp. 1014-1019 ◽  
Author(s):  
Zhi Qiang Gao ◽  
Jin Bao Lan ◽  
Xiao Wei Liu ◽  
Liang Yin
Keyword(s):  
Frequency Synthesizer ◽  
Linear Feedback ◽  
Cmos Process ◽  
Noise Shaping ◽  
Network Applications ◽  
Delta Sigma Modulator ◽  
Multi Stage ◽  
Delta Sigma ◽  
Third Stage ◽  
Feedback Shift Register

This paper presents a design of fractional-N frequency synthesizer with low dithering, which is fabricated in a 130nm CMOS process. A 3rd-order delta-sigma modulator is based on digital multi-stage noise shaping (MASH) structure with its second and third stage dithered by 7-bit linear feedback shift register (LFSR) was designed for the frequency synthesizer, and a long word is used for the first modulator in the MASH structure. The simulation result of the whole frequency synthesizer shows that it can output two-way I/Q signal between 2.28GHz and 2.53GHz, and its spurs are lower than-75dBc.

The Design of a 5 GHz Programmable Frequency Divider for Fractional-N Frequency Synthesizer

2011 ◽  
Vol 341-342 ◽  
pp. 623-628
Author(s):  
Zhong Shan Chen ◽  
Yan Tu ◽  
Liang Feng
Keyword(s):  
High Speed ◽  
Frequency Synthesizer ◽  
Critical Path ◽  
Propagation Delay ◽  
Frequency Divider ◽  
Cmos Process ◽  
5 Ghz ◽  
Work Up ◽  
Timing Requirement ◽  
Programmable Frequency Divider

The design of a high speed programmable frequency divider for fractional-N frequency synthesizer is presented. The programmable divider consists of a divide-by-4/5 dual-modulus prescaler, a 5-bit programmable counter, and a 2-bit swallow counter. A new scheme of reload operation is adopted to reduce the propagation delay of the critical path. The triggering signal for the two counters is selected carefully to mitigate the timing requirement of the mode control signal. The divider is designed in 0.18 um CMOS process. Its division ratio (DR) covers the range from 12 to 127. Post-layout simulations show it can work up to 5 GHz under 1.8 V power supply, while consuming only 9 mW and occupying an area of about 0.06 mm2.

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