scholarly journals Completely first order and tone free partitioned data weighted averaging technique used in a multibit delta sigma modulator

2009 ◽  
Author(s):  
Esmaeil Najafi Aghdam ◽  
Philippe Benabes ◽  
Javad Abbasszadeh
Keyword(s):  
Weighted Averaging ◽  
Averaging Technique ◽  
First Order ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Partitioned Data ◽  
Data Weighted Averaging

scholarly journals Second order noise shaping for data-weighted averaging technique to improve sigma-delta DAC performance

2021 ◽  
Vol 10 (1) ◽  
pp. 79
Author(s):  
Ali Kerem Nahar ◽  
Ansam Subhi Jaddar ◽  
Hussain K. Khleaf ◽  
Mohmmed Jawad Mortada Mobarek
Keyword(s):  
Power Dissipation ◽  
Second Order ◽  
Weighted Averaging ◽  
Noise Shaping ◽  
Sigma Delta ◽  
Averaging Technique ◽  
Delta Sigma ◽  
Low Levels ◽  
Digital To Analog ◽  
Data Weighted Averaging

<p>In general, the noise shaping responses, a cyclic second order response is delivered by the method of data weighted averaging (DWA) in which the output of the digital-to-analog convertor (DAC) is restricted to one of two states. DWA works efficiently for rather low levels of quantizing; it begins presenting considerable difficulties when internal levels of quantizing are extended further. Though, each added bit of internal quantizing causes an exponentially increasing in power dissipation, complexity and size of the DWA logic and the DAC. This gives a controlled seconnd order response accounting for the mismatch of the elements of DAC. The multi-bit DAC is made up of numerous single-bit DACs having values thereof chosen via a digital encoder. This research presents a discussion of the influence of mismatching between unit elements of the Delta-Sigma DAC. This results in a constrained second order response accounting for mismatch of DAC elements. The results of the simulation showed how the effectiveness of DWA method is in reducing band tones. Furthermore, DWA method has proved its efficiency in solving the mismatching of DAC unit elements. The noise of the mismatching elements is enhanced 11 dB at 0.01 with the proposed DWA, thereby enhancing the efficiency of the DAC in comparison to the efficiency of the DAC with no use of the circuit of DWA</p>

A novel structure of dithered nested digital delta sigma modulator with low-complexity low-spur for fractional frequency synthesizers

2016 ◽  
Vol 35 (1) ◽  
pp. 157-171 ◽  
Author(s):  
Seyed Ali Sadat Noori ◽  
Ebrahim Farshidi ◽  
Sirus Sadoughi
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Synthesizers ◽  
Linear Feedback ◽  
Hardware Complexity ◽  
Order Error ◽  
Content Type ◽  
First Order ◽  
Fractional Frequency ◽  
Delta Sigma Modulator ◽  
Delta Sigma

Purpose – Digital Delta Sigma Modulator (DDSM) is used widely in electronic circuits including Radars, class-D power amplifiers and fractional frequency synthesizers. The purpose of this paper is to propose an implementation for MASH DDSMs named as Multi Modulus Reduced Complexity (MMRC) architecture. Design/methodology/approach – This architecture will use a very simple pseudorandom Linear Feedback Shift Register (LFSR) dither signal with period N_d to randomize the digital MMRC modulator used for fractional frequency synthesizers. Using error masking methodology, the MMRC modulator can decrease the hardware consumption and increase accuracy of the fractional frequency synthesizer. Rules for selecting the appropriate word lengths of the constituent MMRC modulator are derived. Findings – This paper contains three modulators. The first stage modulator is a variable modulus First Order Error Feedback Modulator and has a programmable modulus M1 that is not a power of two. The second and third stage modulators are the first order pseudorandom LFSR dithered MASH 1-1 and modified MASH 1-1-1, which have conventional modulo M2, M3, respectively. With optimum selection modulus M1, the new structure can synthesize the desired frequency exactly. Simulation results confirm the theoretical predictions. Also the results of circuit implementation proposed method reports 13 per cent reduction in hardware. Originality/value – This paper for the first time proposes a nested sigma delta modulator with a pseudorandom shaped dither signal which reduced hardware complexity and increased the period of output signal. This modulator is exploited in the fractional frequency synthesizer to the output frequency can be set more accurately.

A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order $\Delta\Sigma$ Modulator in 90-nm CMOS

2009 ◽  
Vol 44 (12) ◽  
pp. 3539-3546 ◽  
Author(s):  
Koji Fukuda ◽  
Hiroki Yamashita ◽  
Fumio Yuki ◽  
Goichi Ono ◽  
Ryo Nemoto ◽  
...  
Keyword(s):  
Phase Detector ◽  
Linear Phase ◽  
Charge Redistribution ◽  
First Order ◽  
Delta Sigma Modulator ◽  
Delta Sigma
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