A Low Offset High Voltage Swing Rail-to-Rail Buffer Amplifier with for LCD Driver

Author(s):  
Guo-Teng Hong ◽  
Chih-Hsiung Shen
2011 ◽  
Vol 20 (07) ◽  
pp. 1377-1387 ◽  
Author(s):  
CHIH-WEN LU ◽  
CHING-MIN HSIAO

A high-speed low-power rail-to-rail buffer amplifier, which is suitable for liquid crystal display driver applications, is proposed. An offset voltage is intentionally built in the second stage to cut off the transistors of last stage from the output node in the stable state and hence achieve low dc power consumption. The input referred offset voltage due to the built-in offset is very small. The buffer draws little current while static but has a large driving capability while transient. An experimental prototype buffer amplifier implemented in a 0.35-μm CMOS technology demonstrates that the circuit can operate under a wide power supply range. Quiescent current of 5 μA is measured. The buffer exhibits the settling time of 1.5 μs for a voltage swing of 0.1 ~ (VDD – 0.1) V under a 600 pF capacitance load. The area of this buffer is 30 × 98 μm2. The measured data show that the proposed output buffer amplifier is very suitable for LCD driver applications.


Author(s):  
Jia-Hui Wang ◽  
Jing-Chuan Qiu ◽  
Hao-Yuan Zheng ◽  
Chien-Hung Tsai ◽  
Chen-Yu Wang ◽  
...  

2010 ◽  
Vol 19 (06) ◽  
pp. 1181-1197 ◽  
Author(s):  
CHIH-WEN LU ◽  
CHING-MIN HSIAO

A compact high-speed low-power rail-to-rail buffer amplifier, which is suitable for driving heavy capacitive loads, is proposed. The buffer amplifier is composed of a pair of push-pull output transistors with two feedback loops consisting of a pair of complementary error amplifiers and a pair of complementary common-source amplifiers. The buffer draws little current while static but has a large driving capability while transient. A mutual bias scheme is also proposed to reduce the power consumption and the die area for LCD applications. An experimental prototype buffer amplifier implemented in a 0.35 μm CMOS technology demonstrates that the settling time is 1.5 μs for a voltage swing of 0.1 ~ (VDD–0.1) V under a 600 pF capacitance load. Quiescent current of 4 μA is measured. The area of this buffer is 32 × 109 μm2.


2011 ◽  
Vol 20 (07) ◽  
pp. 1277-1286 ◽  
Author(s):  
MERIH YILDIZ ◽  
SHAHRAM MINAEI ◽  
EMRE ARSLAN

This work presents a high-slew rate rail-to-rail buffer amplifier, which can be used for flat panel displays. The proposed buffer amplifier is composed of two transconductance amplifiers, two current comparators and a push-pull output stage. Phase compensation technique is also used to improve the phase margin value of the proposed buffer amplifier for different load capacitances. Post-layout simulations of the proposed buffer amplifier are performed using 0.35 μm AMS CMOS process parameters and 3.3 V power supply. The circuit is tested under a 600 pF capacitive load. An average settling time of 0.85 μs under a full voltage swing is obtained, while only 3 μA quiescent current is drawn from the power supply. Monte Carlo analysis is also added to show the process variation effects on the circuit.


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