Bit parallel test pattern generation for path delay faults

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470351 ◽

2002 ◽

Author(s):

M. Henftling ◽

H. Wittman

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay Faults ◽

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Fast test pattern generation for all path delay faults considering various test classes

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246529 ◽

2002 ◽

Author(s):

K. Fuchs ◽

H.C. Wittmann ◽

K.J. Antreich

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay Faults

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DYNAMITE: an efficient automatic test pattern generation system for path delay faults

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.88928 ◽

1991 ◽

Vol 10 (10) ◽

pp. 1323-1335 ◽

Author(s):

K. Fuchs ◽

F. Fink ◽

M.H. Schulz

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Delay Faults ◽

Path Delay Faults ◽

Generation System ◽

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Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions

2009 27th IEEE VLSI Test Symposium ◽

10.1109/vts.2009.22 ◽

2009 ◽

Author(s):

Edward Flanigan ◽

Spyros Tragoudas ◽

Arkan Abdulrahman

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay Faults ◽

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RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.331411 ◽

1994 ◽

Vol 13 (12) ◽

pp. 1550-1562 ◽

Author(s):

K. Fuchs ◽

M. Pabst ◽

T. Rossel

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay Faults ◽

Generation Algorithm

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Test pattern generation for path delay faults in synchronous sequential circuits using multiple fast clocks and multiple observation times

Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing ◽

10.1109/ftcs.1994.315617 ◽

2002 ◽

Author(s):

P. Uppaluri ◽

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Pattern ◽

Sequential Circuits ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay Faults ◽

Synchronous Sequential Circuits ◽

Observation Times

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Function-based compact test pattern generation for path delay faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2005.853607 ◽

2005 ◽

Vol 13 (8) ◽

pp. 996-1001 ◽

Author(s):

M.K. Michael ◽

S. Tragoudas

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay Faults ◽

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Advanced automatic test pattern generation techniques for path delay faults

[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers ◽

10.1109/ftcs.1989.105541 ◽

2003 ◽

Author(s):

M.H. Schulz ◽

K. Fuchs ◽

F. Fink

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Delay Faults ◽

Path Delay Faults ◽

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Parallel test pattern generation using circuit partitioning in a shared-memory multiprocessor

Lecture Notes in Computer Science - Applied Parallel Computing Large Scale Scientific and Industrial Problems ◽

10.1007/bfb0095334 ◽

1998 ◽

pp. 167-171 ◽

Author(s):

Consolación Gil ◽

Julio Ortega ◽

Jose Luis Bernier ◽

Maria Dolores Gil

Keyword(s):

Shared Memory ◽

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Circuit Partitioning ◽

Parallel Test ◽

Shared Memory Multiprocessor

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A partitioning and storage based built-in test pattern generation method for delay faults in scan circuits

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). ◽

10.1109/ats.2002.1181696 ◽

2003 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Scan Circuits ◽

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Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults

2010 23rd International Conference on VLSI Design ◽

10.1109/vlsi.design.2010.30 ◽

2010 ◽

Author(s):

Shehzad Hasan ◽

Ajoy K. Palit ◽

Walter Anheier

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

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