Analysis of entire power distribution system of chip, package and board for high speed IO design

Nowadays, there are various signal processing methods that have been studied by many researchers in order to detect faults in power lines. From previous literature, signal processing that works based on time frequency analysis has been proven to accurately detect faults at high speed. In this study, wavelet transform is adopted to analyse fault occurrences on power line of distribution network. Three types of faults due to lightning, switching and short circuit fault were analysed based on their voltage waveform profiles. ‘Daubechies’ 4 (db4) mother wavelet and four levels decomposition were implemented to extract the features. Approximation at level 4 (A4) and detail coefficient at level 1 to 4 (D1-D4) were extracted to evaluate the energy, skewness, and kurtosis. Based on the results, lightning showed the highest energy, skewness and kurtosis compared to the short circuit and switching voltage waveform. Therefore, these features can be utilized as the new parameters for fault detection in a power system network

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Measurement of Differential Mode Impedance and Longitudinal Conversion Loss for In-Factory High-Speed PLC System using Three-Phase Power Distribution System

2020 IEEE International Symposium on Power Line Communications and its Applications (ISPLC) ◽

10.1109/isplc48789.2020.9115393 ◽

2020 ◽

Author(s):

Toshiyuki Wakisaka ◽

Tohlu Matsushima ◽

Hiroyuki Okumura ◽

Hisao Koga ◽

Nobuo Kuwabara ◽

...

Keyword(s):

Power Distribution ◽

Distribution System ◽

High Speed ◽

Differential Mode ◽

Conversion Loss ◽

Power Distribution System ◽

Three Phase

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Powering the Trains

ASME 2012 Rail Transportation Division Fall Technical Conference ◽

10.1115/rtdf2012-9414 ◽

2012 ◽

Author(s):

Michel A. Thomet

Keyword(s):

Power Distribution ◽

Distribution System ◽

High Speed ◽

High Performance ◽

Real Life ◽

Power Distribution System ◽

Life Project ◽

Control Precision ◽

Rail Line ◽

The Impact

Electric trains exhibit some of the highest performance among all surface modes of transportation in terms of speed, acceleration, control precision and reliability. This is so because of the very large amount of power that can be delivered to each train by means of a third rail or an overhead wire. Also, like all rail vehicles, trains have a very small friction/drag to overcome, even at high speed. To make this high performance possible, the train power distribution system has to be designed so that it can be highly reliable and deliver the power to the trains even when some of the systems components are out or are degraded. Because of the complexity of the power distribution system, a simulation approach is generally followed to model the trains operating in different modes and headways under different component failure scenarios. This process is illustrated using a real life project, namely the Dulles Corridor Metrorail project. A Bechtel proprietary simulation program is used to model the new rail line. A series of failure scenarios is investigated and the impact on train operations is evaluated. The purpose of this exercise was to verify that the systems components have been properly sized and specified.

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An FPGA Based Novel Digital Controller for DSTATCOM to Enhance Power Quality in Distribution System

ECTI Transactions on Electrical Engineering, Electronics, and Communications ◽

10.37936/ecti-eec.2020182.240340 ◽

2020 ◽

Vol 18 (2) ◽

pp. 118-129

Author(s):

Gokulananda Sahu ◽

Rajesh Kumar Patjoshi ◽

Rakhee Panigrahi

Keyword(s):

Power Distribution ◽

Distribution System ◽

High Speed ◽

Reactive Power ◽

Low Cost ◽

Digital Controller ◽

Control Technique ◽

Positive Sequence ◽

Steady State Condition ◽

Power Distribution System

This paper proposes an FPGA based all-on-chip novel digital controller for DSTATCOM to compensate harmonics and reactive power existing in power distribution system. The proposed technique extracts reference current by considering instantaneous symmetrical component active power (ISCAP) theory based phase delay compensation (PDC) control technique. The proposed controller comprises positive sequence detector, PI-controller, low-pass filters (LPF) and hysteresis current controller. All these segments are configured on high speed, low cost field programmable gate arrays (FPGA) hardware resources intended to mitigate harmonics and compensate reactive power in power distribution network. Very high speed hardware description language (VHDL) implementation for each module are produced through system generator and implemented on SPARTAN-3 XC3S5000 FPGA chip through RT-XSG toolbox in Opal-RT platform. The performance of proposed controller is demonstrated through VHDL test bench, simulation and real-time experimental results with consideration of total harmonic distortion (THD) and power factor correction in steady state condition.

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