Processing-in-memory in High Bandwidth Memory (PIM-HBM) Architecture with Energy-efficient and Low Latency Channels for High Bandwidth System

Networking connectivity is increasingly based on wireless network technologies, especially in developing nations where the wired network infrastructure is not accessible to a large segment of the population. Wireless data network technologies based on 2G and 3G are quite common globally; 4G-based deployments are on the rise during the past few years. At the same time, the increasing high-bandwidth and low-latency requirements of mobile applications has propelled the Third Generation Partnership Project (3GPP) standards organization to develop standards for the next generation of mobile networks, based on recent advances in wireless communication technologies. This standard is called the Fifth Generation (5G) wireless network standard. This paper presents a high-level overview of the important architectural components, of the advanced communication technologies, of the advanced networking technologies such as Network Function Virtualization and other important aspects that are part of the 5G network standards. The paper also describes some of the common future generation applications that require low-latency and high-bandwidth communications.

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Low-Latency Energy-Efficient Cyber-Physical Disaster System Using Edge Deep Learning

Proceedings of the 21st International Conference on Distributed Computing and Networking ◽

10.1145/3369740.3372752 ◽

2020 ◽

Cited By ~ 1

Author(s):

Yashwant Singh Patel ◽

Sourasekhar Banerjee ◽

Rajiv Misra ◽

Sajal K. Das

Keyword(s):

Deep Learning ◽

Energy Efficient ◽

Low Latency ◽

Disaster System

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FOSquare: A Novel Optical HPC Interconnect Network Architecture Based on Fast Optical Switches with Distributed Optical Flow Control

Photonics ◽

10.3390/photonics8010011 ◽

2021 ◽

Vol 8 (1) ◽

pp. 11

Author(s):

Fulong Yan ◽

Changshun Yuan ◽

Chao Li ◽

Xiong Deng

Keyword(s):

Flow Control ◽

Network Architecture ◽

Network Performance ◽

Optical Switches ◽

Low Power Consumption ◽

Low Latency ◽

High Bandwidth ◽

Fast Flow ◽

Real Traffic ◽

Interconnect Network

Interconnecting networks adopting Fast Optical Switches (FOS) can achieve high bandwidth, low latency, and low power consumption. We propose and demonstrate a novel interconnecting topology based on FOS (FOSquare) with distributed fast flow control which is suitable for HPC infrastructures. We also present an Optimized Mapping (OPM) algorithm that maps the most communication-related processes inside a rack. We numerically investigate and compare the network performance of FOSquare with Leaf-Spine under real traffic traces collected by running multiple applications (CG, MG, MILC, and MINI_MD) in an HPC infrastructure. The numerical results show that the FOSquare can reduce >10% latency with respect to Leaf-Spine under the scenario of 16 available cores.

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FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2021.3059518 ◽

2021 ◽

Vol 29 (4) ◽

pp. 716-729

Author(s):

Alberto Marchisio ◽

Vojtech Mrazek ◽

Muhammad Abdullah Hanif ◽

Muhammad Shafique

Keyword(s):

Energy Efficient ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Low Latency

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NanoLEDs for energy-efficient and gigahertz-speed spike-based sub-λ neuromorphic nanophotonic computing

Nanophotonics ◽

10.1515/nanoph-2020-0177 ◽

2020 ◽

Vol 9 (13) ◽

pp. 4149-4162 ◽

Cited By ~ 2

Author(s):

Bruno Romeira ◽

José M. L. Figueiredo ◽

Julien Javaloyes

Keyword(s):

Neural Networks ◽

Energy Efficient ◽

High Speed ◽

Dynamic Properties ◽

Optical Computing ◽

Differential Conductance ◽

Rate Equations ◽

Dynamical Equations ◽

Electrical Modulation ◽

High Bandwidth

AbstractEvent-activated biological-inspired subwavelength (sub-λ) photonic neural networks are of key importance for future energy-efficient and high-bandwidth artificial intelligence systems. However, a miniaturized light-emitting nanosource for spike-based operation of interest for neuromorphic optical computing is still lacking. In this work, we propose and theoretically analyze a novel nanoscale nanophotonic neuron circuit. It is formed by a quantum resonant tunneling (QRT) nanostructure monolithic integrated into a sub-λ metal-cavity nanolight-emitting diode (nanoLED). The resulting optical nanosource displays a negative differential conductance which controls the all-or-nothing optical spiking response of the nanoLED. Here we demonstrate efficient activation of the spiking response via high-speed nonlinear electrical modulation of the nanoLED. A model that combines the dynamical equations of the circuit which considers the nonlinear voltage-controlled current characteristic, and rate equations that takes into account the Purcell enhancement of the spontaneous emission, is used to provide a theoretical framework to investigate the optical spiking dynamic properties of the neuromorphic nanoLED. We show inhibitory- and excitatory-like optical spikes at multi-gigahertz speeds can be achieved upon receiving exceptionally low (sub-10 mV) synaptic-like electrical activation signals, lower than biological voltages of 100 mV, and with remarkably low energy consumption, in the range of 10–100 fJ per emitted spike. Importantly, the energy per spike is roughly constant and almost independent of the incoming modulating frequency signal, which is markedly different from conventional current modulation schemes. This method of spike generation in neuromorphic nanoLED devices paves the way for sub-λ incoherent neural elements for fast and efficient asynchronous neural computation in photonic spiking neural networks.

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