Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor

Author(s):  
Hai Yu ◽  
Michael Nicolaidis ◽  
Lorena Anghel ◽  
Nacer-Eddine Zergainoh
2012 ◽  
Vol 52 (9-10) ◽  
pp. 1781-1786 ◽  
Author(s):  
R. Possamai Bastos ◽  
F. Sill Torres ◽  
G. Di Natale ◽  
M. Flottes ◽  
B. Rouzeyre

Author(s):  
Ravi Khatwal ◽  
Manoj Kumar Jain

Recently Low power custom memory design is the major issue for embedded designer. Micro wind and Xilinx simulator performs efficient cache simulation and high performances with low power consumption. SRAM efficiency analyzed with 6-T architecture design and analyzed the simulation performance for specific application. We have implemented clock based memory architecture design and analyzed internal clock efficiency for SRAM. Architectural clock implemented memory design that reduces access time and propagation delay time for embedded devices. Internal semiconductor material improvement increases simulation performance and these design implemented for application specific design architecture.


2016 ◽  
Vol 10 (6) ◽  
pp. 306-314 ◽  
Author(s):  
Soumya Basu ◽  
Pablo Garcia Del Valle ◽  
Georgios Karakonstantis ◽  
Giovanni Ansaloni ◽  
Laura Pozzi ◽  
...  

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