An efficient low power NoC router architecture design

2015 ◽  
Author(s):  
S. Shenbagavalli ◽  
S. Karthikeyan
Keyword(s):  
Low Power ◽  
Architecture Design ◽  
Router Architecture

An Integrated Architectural Clock Implemented Memory Design for Embedded System

2015 ◽  
Vol 4 (2) ◽  
pp. 129
Author(s):  
Ravi Khatwal ◽  
Manoj Kumar Jain
Keyword(s):  
Embedded System ◽  
Low Power ◽  
Propagation Delay ◽  
Internal Clock ◽  
Access Time ◽  
Architecture Design ◽  
Embedded Devices ◽  
Memory Design ◽  
Simulation Performance ◽  
Cache Simulation

Recently Low power custom memory design is the major issue for embedded designer. Micro wind and Xilinx simulator performs efficient cache simulation and high performances with low power consumption. SRAM efficiency analyzed with 6-T architecture design and analyzed the simulation performance for specific application. We have implemented clock based memory architecture design and analyzed internal clock efficiency for SRAM. Architectural clock implemented memory design that reduces access time and propagation delay time for embedded devices. Internal semiconductor material improvement increases simulation performance and these design implemented for application specific design architecture.

scholarly journals Inexact‐aware architecture design for ultra‐low power bio‐signal analysis

2016 ◽  
Vol 10 (6) ◽  
pp. 306-314 ◽  
Author(s):  
Soumya Basu ◽  
Pablo Garcia Del Valle ◽  
Georgios Karakonstantis ◽  
Giovanni Ansaloni ◽  
Laura Pozzi ◽  
...  
Keyword(s):  
Low Power ◽  
Signal Analysis ◽  
Architecture Design ◽  
Ultra Low Power

scholarly journals SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects

2013 ◽  
Vol 21 (8) ◽  
pp. 1432-1446 ◽  
Author(s):  
Jacob Postman ◽  
Tushar Krishna ◽  
Christopher Edmonds ◽  
Li-Shiuan Peh ◽  
Patrick Chiang
Keyword(s):  
Low Power ◽  
Flow Control ◽  
Network On Chip ◽  
Power Network ◽  
Router Architecture ◽  
On Chip
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