Four-quadrant CMOS analog multiplier based on new current squarer circuit with high-speed

Author(s):  
A. Naderi ◽  
H. Mojarrad ◽  
H. Ghasemzadeh ◽  
A. Khoei ◽  
Kh. Hadidi
2009 ◽  
Vol 63 (9) ◽  
pp. 769-775 ◽  
Author(s):  
Ali Naderi ◽  
Abdollah Khoei ◽  
Khayrollah Hadidi ◽  
Hadi Ghasemzadeh

2017 ◽  
Vol 43 (6) ◽  
pp. 2909-2918 ◽  
Author(s):  
Mohammad Moradinezhad Maryan ◽  
Ahmad Ghanaatian ◽  
Seyed Javad Azhari ◽  
Adib Abrishamifar

2020 ◽  
Vol 15 (3) ◽  
pp. 1-12
Author(s):  
Ana Isabela Araújo Cunha ◽  
Antonio José Sobrinho De Sousa ◽  
Edson Pinto Santana ◽  
Robson Nunes De Lima ◽  
Fabian Souza De Andrade ◽  
...  

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.


1985 ◽  
Author(s):  
Klaas Bult ◽  
Hans Wallinga

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