A four-quadrant analog multiplier under a single power supply voltage

2011 ◽  
Vol 71 (3) ◽  
pp. 525-530 ◽  
Author(s):  
Xiaobing Tao ◽  
Chao Liu ◽  
Tao Zhao
2011 ◽  
Vol E94-C (6) ◽  
pp. 1072-1075
Author(s):  
Tadashi YASUFUKU ◽  
Yasumi NAKAMURA ◽  
Zhe PIAO ◽  
Makoto TAKAMIYA ◽  
Takayasu SAKURAI

2016 ◽  
Vol E99.C (10) ◽  
pp. 1219-1225
Author(s):  
Masahiro ISHIDA ◽  
Toru NAKURA ◽  
Takashi KUSAKA ◽  
Satoshi KOMATSU ◽  
Kunihiro ASADA

1993 ◽  
Vol 29 (15) ◽  
pp. 1324 ◽  
Author(s):  
L.E. Larson ◽  
M.M. Matloubian ◽  
J.J. Brown ◽  
A.S. Brown ◽  
M. Thompson ◽  
...  

2020 ◽  
Vol 15 (3) ◽  
pp. 1-12
Author(s):  
Ana Isabela Araújo Cunha ◽  
Antonio José Sobrinho De Sousa ◽  
Edson Pinto Santana ◽  
Robson Nunes De Lima ◽  
Fabian Souza De Andrade ◽  
...  

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.


2020 ◽  
Vol 67 (5) ◽  
pp. 811-817
Author(s):  
G. Torrens ◽  
A. Alheyasat ◽  
B. Alorda ◽  
S. Barcelo ◽  
J. Segura ◽  
...  

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