Compact CMOS Analog Multiplier Free of Voltage Reference Generators

2020 ◽  
Vol 15 (3) ◽  
pp. 1-12
Author(s):  
Ana Isabela Araújo Cunha ◽  
Antonio José Sobrinho De Sousa ◽  
Edson Pinto Santana ◽  
Robson Nunes De Lima ◽  
Fabian Souza De Andrade ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Harmonic Distortion ◽  
Current Mode ◽  
Input Voltage ◽  
Voltage Reference ◽  
Analog Multiplier ◽  
Voltage Range ◽  
Voltage Variation ◽  
Static Power ◽  
Four Quadrant

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.

FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS

2012 ◽  
Vol 21 (03) ◽  
pp. 1250024 ◽  
Author(s):  
CHAIWAT SAKUL ◽  
KOBCHAI DEJHAN
Keyword(s):  
Relative Error ◽  
Low Voltage ◽  
Harmonic Distortion ◽  
Input Voltage ◽  
Experimental Result ◽  
Voltage Range ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
Power Dispersion ◽  
Four Quadrant

This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.

scholarly journals An Analogue Multiplier using CNTFET Technology

2020 ◽  
Vol 19 ◽  
Keyword(s):  
Analog Circuits ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Analog Multiplier ◽  
Effect Transistor ◽  
Four Quadrant ◽  
Better Than

The endeavor to overcome problems of complementary metal oxide semiconductor technology makes the advent of Carbon nanotube field effect transistor (CNTFET). Improvement of structure transistor CNTFET makes higher mobility and electrostatics of gate electrons. Therefore, many analog circuits are now designed based on CNTFET technology. This paper presents a low power current mode four-quadrant analog multiplier based on CNTFET and CMOS technologies. All simulations were done with the synopsys Hspice simulator using 32nm CNTFET model from Stanford University and 32nm CMOS from PTM library at a supply voltage of 3.3 v. It was shown that the simulation of a multiplier based on CNTFET technology performs better than a multiplier based on CMOS technology.

Implementation of Single-Phase Two-Switch Midpoint Unidirectional Multilevel Converter System

2018 ◽  
Vol 19 (4) ◽  
Author(s):  
Peethala Rajiv Roy ◽  
P. Parthiban ◽  
B. Chitti Babu
Keyword(s):  
Single Phase ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Input Voltage ◽  
Open Loop ◽  
Current Control ◽  
Control Technique ◽  
Control Scheme

Abstract This paper deals with implementation of a single-phase three level converter system under low voltage condition. The frequency of the switches is made constant and involves change in ${t_{on}}$ and ${t_{off}}$ duration. For this condition the pulse width modulation control scheme for a single phase three level rectifier is developed to improve the power quality. The hysteresis current control technique is adopted to bring forth three-level PWM on the dc side of the bridge rectifier and to achieve high power factor and low harmonic distortion. Based on the proposed control scheme, the line current is driven to follow the sinusoidal current command which is in phase with the supply voltage. By using three-level voltage pattern the blocking voltage of each power device is clamped to half of the dc link voltage. The simulation and experimental results of 20W converter under low input voltage condition are shown to verify the circuit performance. Open loop simulation and hardware tests are implemented by applying a low voltage of 15 V(rms) on the input side.

A High Temperature 4H-SiC Voltage Reference for Depletion Mode GaN-Based Circuits

2017 ◽  
Vol 2017 (HiTEN) ◽  
pp. 000118-000121
Author(s):  
ZiHao Zhang ◽  
Jebreel M. Salem ◽  
Dong Sam Ha
Keyword(s):  
High Temperature ◽  
High Temperatures ◽  
Oil And Gas ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Voltage Reference ◽  
Voltage Range ◽  
Oil And Gas Exploration ◽  
Low Leakage ◽  
Temperature Applications

Abstract High temperature electronics are highly demanded for many applications such as automotive, space, and oil and gas exploration. Electronic circuits for those applications are required to operate reliably without using bulky cooling systems. Circuits based on silicon (Si) suffer from high leakage currents at high temperatures. Silicon Carbide (SiC) circuits, on the other hand, are suitable for high temperature applications due to the wide bandgap and offer high breakdown voltage and low leakage current. This paper presents a negative voltage reference for high temperature applications using commercial-off-the-shelf (COTS) 4H-SiC transistors. The proposed voltage reference adopts Widlar bandgap reference topology, and it aims to provide a negative reference voltage for Gallium Nitride (GaN) circuits operating at high temperatures. Measurement results indicate that the proposed circuit provides a negative reference voltage with a low temperature coefficient of 42 ppm/°C for temperatures ranging from 25 °C to 250 °C. The proposed circuit also operates reliably for a wide supply voltage range of −7.5 V to −15 V for the temperature range.

Integrated Bandgap Voltage Reference for High Voltage Vehicle Applications

2015 ◽  
Vol 24 (08) ◽  
pp. 1550125 ◽  
Author(s):  
Sergio Saponara
Keyword(s):  
High Voltage ◽  
Low Voltage ◽  
Supply Voltage ◽  
Input Voltage ◽  
Voltage Reference ◽  
Temperature Drift ◽  
Power Supply Rejection Ratio ◽  
Compact Size ◽  
Electrical Vehicles ◽  
Bandgap Voltage Reference

This work presents a bandgap voltage reference (BGR) integrated in 0.25-μm bipolar-CMOS-DMOS (BCD) technology. The BGR circuit generates a reference voltage of 1.22 V. It is able to withstand large supply voltage variations of vehicle applications from 4.5 V, e.g., in case of cranking, up to 60-V, maximum value in case of emerging 48-V battery systems for hybrid and electrical vehicles. The circuit has an embedded high-voltage (HV) pseudo-regulator block that provides a more stable internal supply rail for a cascaded low-voltage bandgap core. HV MOS are used only in the pre-regulator block thus allowing the design of a BGR with compact size. The proposed architecture permits to withstand large input voltage variations with a temperature drift of a hundred of ppm/°C, a line regulation (LR) of few mV/V versus the external supply voltage and a power supply rejection ratio (PSRR) higher than 90 dB.

scholarly journals CMOS Voltage Reference using a Self-Cascode Composite Transistor and a Schottky Diode

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1271
Author(s):  
Brito ◽  
Colombo ◽  
Moreno ◽  
El-Sankary
Keyword(s):  
Schottky Diode ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Silicon Area ◽  
Circuit Topology ◽  
Voltage Range ◽  
Self Cascode ◽  
Cmos Voltage Reference ◽  
The Impact

This work presents an investigation of the temperature behavior of self-cascode composite transistors (SCCTs). Results supported by silicon measurements show that SCCTs can be used to generate a proportional to absolute temperature voltage or even a temperature-compensated voltage. Based on the achieved results, a new circuit topology of a resistorless voltage reference circuit using a Schottky diode is also presented. The circuit was fabricated in a 130 nm BiCMOS process and occupied a silicon area of 67.98 µm × 161.7 µm. The averaged value of the output voltage is 720.4 mV, and its averaged line regulation performance is 2.3 mV/V, calculated through 26 characterized chip samples. The averaged temperature coefficient (TC) obtained through five chip samples is 56 ppm/°C in a temperature range from −40 to 85°C. A trimming circuit is also included in the circuit topology to mitigate the impact of the fabrication process effects on its TC. The circuit operates with a supply voltage range from 1.1 to 2.5 V.

scholarly journals A 1 V 92 dB SNDR 10 kHz Bandwidth Second-Order Asynchronous Delta-Sigma Modulator for Biomedical Signal Processing

Sensors ◽  
2020 ◽  
Vol 20 (15) ◽  
pp. 4137
Author(s):  
Vilém Kledrowetz ◽  
Lukáš Fujcik ◽  
Roman Prokop ◽  
Jiří Háze
Keyword(s):  
Signal Processing ◽  
Supply Voltage ◽  
Input Voltage ◽  
General Purpose ◽  
Second Order ◽  
Biomedical Signal Processing ◽  
Center Frequency ◽  
Voltage Range ◽  
Delta Sigma Modulator ◽  
Delta Sigma

In this paper, a second-order asynchronous delta-sigma modulator (ADSM) is proposed based on the active-RCintegrators. The ADSM is implemented in the 0.18 μ m CMOS Logic or Mixed-Signal/RF, General Purpose process from the Taiwan Semiconductor Manufacturing Company with a center frequency of 848 kHz at a supply voltage of 1 V with a 92 dB peak signal-to-noise and distortion ratio ( S N D R ), which corresponds to 15 bit resolution. These parameters were achieved in all the endogenous bioelectric signals bandwidth of 10 kHz. The ADSM dissipated 295 μ W and had an area of 0.54 mm 2 . The proposed ADSM with a high resolution, wide bandwidth, and rail-to-rail input voltage range provides the universal solution for endogenous bioelectric signal processing.

scholarly journals Optimization of PFC SEPIC Converter Parameters Design for Minimization of THD and Voltage Ripple

2018 ◽  
Vol 7 (4.30) ◽  
pp. 240 ◽  
Author(s):  
M. K. R. Noor ◽  
A. Ponniran ◽  
M. A. Z. A. Rashid ◽  
A. A. Bakar ◽  
J. N. Jumadril ◽  
...  
Keyword(s):  
Design Optimization ◽  
Output Voltage ◽  
Harmonic Distortion ◽  
Input Voltage ◽  
Switching Frequency ◽  
Unity Power Factor ◽  
Voltage Ripple ◽  
Voltage Variation ◽  
Balancing Energy ◽  
Energy Compensation

This paper discusses the current total harmonic distortion (THDi) and voltage ripple minimization of SEPIC converter based on parameters design optimization. This conventional PFC SEPIC converter is designed to operate in discontinuous conduction mode in order to achieve almost unity power factor. The passive components, i.e., inductor and capacitor are designed based on switching frequency and resonant frequency. Meanwhile, the ranges of duty cycle for buck and boost operations are between 0<D<0.5 and 0.5<D<1, respectively, for the output voltage variation of the converter. The principle of the parameters design optimization is based on the balancing energy compensation between the input capacitor and output inductor. The experimental results show that, the current THD is reduced to 2.66% from 70.9% after optimization process is conducted. Furthermore, it is confirmed that the output voltage ripple frequency is always double from the input line frequency, fL = 2foutand the output voltage ripple is always lower than the maximum input voltage ripple. Therefore, the designed parameters of the experimental converter is confirmed with approximately 65 W of the converter output power.

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