Over the last several years, uniprocessor systems, in an effort to overcome the limits of deeperpipelining, instruction-level parallelism and power dissipation, evolved from one processing coreto tens or hundreds of cores. At the same time, multi-chip systems and Systems on Board (SoB),have started giving their place to Systems on Chip (SoC) that exploit the latest nanometertechnologies. This has also caused a tremendous shift in the system development process towardsembedded systems, hardware/software co-design, SoC designs, multi-core designs, and hardwareaccelerators. Nowadays, one of the key issues for continued performance scaling is thedevelopment of advanced CAD tools that can efficiently support the design and verification ofthese new platforms and the requirements of today’s complex applications. This thesis focuses on three important aspects of the system development process: hardware/software partitioning, simulation and verification. Since the time consumed in those tasks is usually a large percentage of the overall development time, speeding them up can significantly reduce the ever important time to market. Hardware emulation on FPGAs has been widely used as a significantly faster and moreaccurate approach for the verification of complex designs than software simulation. In this approach, Hardware Simulation Accelerator and Emulator co-processor units are used to offloadcalculation-intensive tasks from software simulators. One of the biggest problems however is thatthe communication overhead between the software simulator, where the behavioral testbenchusually runs, and the hardware emulator where the Design Under Test (DUT) is emulated, isbecoming a new critical bottleneck. Another problem is that in a hardware emulation environmentit is impossible to bring outside of the chip a large number of internal signals for verificationpurposes. Therefore, on-chip observability has become a significant issue. Finally, one more crucial issue is the decision that has to be made on how to partition the system components into two distinct sets: those that will be implemented in hardware and those that will run in software. Inthis thesis we analyze all the aforementioned problems and propose novel techniques that can beused to attack them. First, we introduce a novel emulation framework that automatically transforms certain HDL parts of the testbench into synthesizable code in order to offload them from the software simulator and, more importantly, minimize the aforementioned communication overhead. In particular, we partition the testbench running on the software simulator into two sections: the testbench HDL code that communicates directly with the DUT and the rest, C-like, testbench code. The former section is transformed into synthesizable code while the latter runs in a general purpose CPU. Next, we extend this architecture by adding multiple fast scan-chain paths in the design in order to provide full circuit observability and controllability on the fly. Finally, we develop a fullyautomated hardware/software partitioning tool that incorporates a novel flow with new costmetrics and functions to provide fast and efficient solutions. The tool employs two separatepartitioning algorithms; Simulated Annealing (SA) and a novel greedy algorithm, the GroupingMapping Partitioning (GMP). Our experiments demonstrate that our methodologies provide cost-effective solutions for the hardware/software partitioning and emulation of large and complex systems.
Novel techniques for hardware / software partitioning and emulation
