Bit-serial pipeline synthesis for multi-FPGA systems with C++ design capture

1996 ◽  
Author(s):  
Isshiki ◽  
Dai
Keyword(s):  
Bit Serial ◽  
Design Capture

Division and bit-serial multiplication over GF(qm)

1992 ◽  
Vol 139 (3) ◽  
pp. 230 ◽  
Author(s):  
M.A. Hasan ◽  
V.K. Bhargava
Keyword(s):  
Bit Serial

Bit-serial systolic sorting: general complexities and an implementation in VLSI

1987 ◽  
Vol 134 (3) ◽  
pp. 125
Author(s):  
H.F. Li ◽  
R. Jayakumar ◽  
X. Sun
Keyword(s):  
Bit Serial

scholarly journals Six shades lighter: a bit-serial implementation of the AES family

2021 ◽  
Author(s):  
Sergio Roldán Lombardía ◽  
Fatih Balli ◽  
Subhadeep Banik
Keyword(s):  
Block Cipher ◽  
Block Ciphers ◽  
Authenticated Encryption ◽  
Current Standard ◽  
Asic Circuit ◽  
The Family ◽  
Encryption And Decryption ◽  
Preliminary Version ◽  
Reduction In Area ◽  
Bit Serial

AbstractRecently, cryptographic literature has seen new block cipher designs such as , or that aim to be more lightweight than the current standard, i.e., . Even though family of block ciphers were designed two decades ago, they still remain as the de facto encryption standard, with being the most widely deployed variant. In this work, we revisit the combined one-in-all implementation of the family, namely both encryption and decryption of each as a single ASIC circuit. A preliminary version appeared in Africacrypt 2019 by Balli and Banik, where the authors design a byte-serial circuit with such functionality. We improve on their work by reducing the size of the compact circuit to 2268 GE through 1-bit-serial implementation, which achieves 38% reduction in area. We also report stand-alone bit-serial versions of the circuit, targeting only a subset of modes and versions, e.g., and . Our results imply that, in terms of area, and can easily compete with the larger members of recently designed family, e.g., , . Thus, our implementations can be used interchangeably inside authenticated encryption candidates such as , or in place of .

Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM

2020 ◽  
Author(s):  
Khalid Al-Hawaj ◽  
Olalekan Afuye ◽  
Shady Agwa ◽  
Alyssa Apsel ◽  
Christopher Batten
Keyword(s):  
In Situ Processing ◽  
Bit Serial

Efficient Design Module Capture and Representation for Product Family Reuse

2017 ◽  
Vol 17 (3) ◽  
Author(s):  
Michael Lundin ◽  
Erik Lejon ◽  
Andreas Dagman ◽  
Mats Näsström ◽  
Peter Jeppsson
Keyword(s):  
Computer Aided Design ◽  
Business Models ◽  
Product Family ◽  
Product Lifecycle Management ◽  
Cad Model ◽  
Efficient Design ◽  
Complex Design ◽  
Computer Aided ◽  
Plm System ◽  
Design Capture

New business models and more integrated product development processes require designers to make use of knowledge more efficiently. Capture and reuse are means of coping, but support, techniques, and mechanisms have yet to be sufficiently addressed. This paper consequently explores how computer-aided technologies (CAx) and a computer-aided design (CAD) model-oriented approach can be used to improve the efficiency of design module capture and representation for product family reuse. The first contribution of this paper is the investigation performed at a Swedish manufacturing company and a set of identified challenges related to design capture and representation for reuse in product family development. The second contribution is a demonstrated and evaluated set of systems and tools, which exemplifies how these challenges can be approached. Efficient design capture is achieved by a combination of automated and simplified design capture, derived from the design implementation (CAD model definition) to the extent possible. Different design representations can then be accessed by the designer using the CAD-internal tool interface. A web application is an example of more general-purpose representation to tailor design content, all of which is managed by a product lifecycle management (PLM) system. Design capture is based on a modular view block definition, stored in formal information models, management by a PLM system, for consistent and reliable design content. It was, however, introduced to support the rich and expressive forms of capture and representation required to facilitate understanding, use, and reuse of varied and increasingly complex designs. A key element in being able to describe a complex design and its implementation has been capture and representation of a set of design states. The solution has been demonstrated to effectively be able to capture and represent significant portions of a step-by-step design training material and the implementation of complex design module through a set of design decisions taken. The validity and relevance of the proposed solution is strengthened by the level of acceptance and perceived value from experienced users, together with the fact that the company is implementing parts of it today.

Firmware Design Capture

1995 ◽  
Author(s):  
Michael J. Viste ◽  
David M. Cannon
Keyword(s):  
Design Activity ◽  
Specific Information ◽  
Frequent User ◽  
Design Information ◽  
Strategic Design ◽  
Quality Feedback ◽  
Development Life Cycle ◽  
Initial Work ◽  
Increase Product Quality ◽  
Design Capture

Abstract One of Allen-Bradley’s goals is leveraging — taking better advantage of existing resources. We are developing a methodology and supporting tools that help engineers share and reuse (i.e., leverage) their firmware design and development work. Writing reusable firmware source code is especially difficult due to the tight constraints in most embedded systems — code must usually be written for product specific hardware needs and resources. Reuse of engineering work at the design level is a more effective approach. With this in mind, we have been working with Allen-Bradley Power Products engineers and managers to pilot a Firmware Design Capture (FDC) system. In a FDC system, engineers work in their own paper or electronic workbooks compiling descriptions of their domains’ technologies and algorithms in loosely structured electronic document sets called technology books. Product-specific information is placed in complementary document sets called product books. Engineers can access this growing body of ‘Strategic Design Information’ that they and others have created; freely drawing from, commenting on, or adding to it. Key characteristics of this FDC system are: • A focus on collecting reusable and accessible design information • Incremental, small-grained development of documents during design activity • Electronic format of documents, for ease of refinement and access • Unobtrusive tools and methods, determined through frequent user feedback We expect this methodology to help engineers improve schedule predictability and reduce the firmware development life cycle, better retain vital technologies and product data, and increase product quality. Feedback from our initial work supports these expectations.

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