Secure authentication of any
Internet-of-Things (IoT)
device becomes the utmost necessity due to the lack of specifically designed IoT standards and intrinsic vulnerabilities with limited resources and heterogeneous technologies. Despite the suitability of
arbiter physically unclonable function (APUF)
among other PUF variants for the IoT applications, implementing it on
field-programmable gate arrays (FPGAs)
is challenging. This work presents the complete characterization of the
path changing switch (PCS)
1
based APUF on two different families of FPGA, like Spartan-3E (90 nm CMOS) and Artix-7 (28 nm CMOS). A comprehensive study of the existing tuning concept for
programmable delay logic (PDL)
based APUF implemented on FPGA is presented, leading to establishment of its practical infeasibility. We investigate the entropy, randomness properties of the PCS based APUF suitable for practical applications, and the effect of temperature variation signifying the adequate tolerance against environmental variation. The XOR composition of PCS based APUF is introduced to boost performance and security. The robustness of the PCS based APUF against machine learning based modeling attack is evaluated, showing similar characteristics as the conventional APUF. Experimental results validate the efficacy of PCS based APUF with a little hardware footprint removing the paucity of lightweight security primitive for IoT.
Why Attackers Lose: Design and Security Analysis of Arbitrarily Large XOR Arbiter PUFs