Review on Domino Logic Techniques for High Speed Low-Power Logic Circuit Application

2019 ◽  
Author(s):  
T. Vinoth Bala ◽  
P. L. Rishi ◽  
R. Sharuya ◽  
N. Subashree ◽  
M. Sneha ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Circuit ◽  
Domino Logic ◽  
Low Power Logic

Design of Low Power and High Speed VLSI Domino Logic Circuit

2018 ◽  
Author(s):  
Praveen J ◽  
Aishwarya Aishwarya ◽  
Jagadish Venkatraman Naik ◽  
Kshithija Kshithija ◽  
Mahesh Biradar
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Circuit ◽  
Domino Logic

scholarly journals Ultra Low Power High Speed Domino Logic Circuit by Using FinFET Technology

2016 ◽  
Vol 14 (1) ◽  
Author(s):  
Ajay Kumar Dadoria ◽  
Kavita Khare ◽  
Tarun Kumar Gupta ◽  
R. P. Singh
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Circuit ◽  
Domino Logic ◽  
Ultra Low Power

scholarly journals Current Comparison Domino based CHSK Domino Logic Technique for Rapid Progression and Low Power Alleviation

2017 ◽  
Vol 7 (5) ◽  
pp. 2468 ◽  
Author(s):  
J. Muralidharan ◽  
P. Manimegalai
Keyword(s):  
Low Power ◽  
Performance Improvement ◽  
High Speed ◽  
Noise Immunity ◽  
Performance Metrics ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Rapid Progression ◽  
Domino Logic ◽  
Rapid Process

The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the parasitic capacitance, which reduces on the dynamic node for robust and rapid process of the circuit. The proposed domino logic is designed with keeper and without keeper to measure the performance metrics of the circuit. The outcomes of the proposed domino logic are better when compared to the existing domino logic circuits. The simulation of the proposed CHSK based on the CCD logic circuit is carried out in Cadence Virtuoso tool.

High-Speed, Low-Power Logic ICs using Quasi-Normally-Off GaAs MESFETs

1980 ◽  
Author(s):  
G. Nuzillat ◽  
G. Bert ◽  
F. Damay-Kavala ◽  
C. Arnodo
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Power Logic

scholarly journals Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

2008 ◽  
Vol 29 (10) ◽  
pp. 1094-1097 ◽  
Author(s):  
G. Dewey ◽  
M.K. Hudait ◽  
Kangho Lee ◽  
R. Pillarisetty ◽  
W. Rachmady ◽  
...  
Keyword(s):  
Quantum Well ◽  
Low Power ◽  
High Speed ◽  
Carrier Transport ◽  
High Mobility ◽  
Performance Impact ◽  
And Performance ◽  
Low Power Logic
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