Performance and power consumption analysis of memory efficient 3D network-on-chip architecture

2013 ◽  
Author(s):  
Xiao Yu ◽  
Li Li ◽  
Yuang Zhang ◽  
Hongbing Pan ◽  
Shuzhuan He
Keyword(s):  
Power Consumption ◽  
Network On Chip ◽  
3D Network ◽  
On Chip ◽  
Memory Efficient

Exploring DRAM Last Level Cache for 3D Network-on-Chip Architecture

2011 ◽  
Vol 403-408 ◽  
pp. 4009-4018 ◽  
Author(s):  
Thomas Can Hao Xu ◽  
Pasi Liljeberg ◽  
Hannu Tenhunen
Keyword(s):  
Power Consumption ◽  
Random Access ◽  
Random Access Memory ◽  
Network On Chip ◽  
Access Memory ◽  
Advantages And Disadvantages ◽  
3D Network ◽  
Sram Design ◽  
On Chip ◽  
The Impact

In this paper, we implement and analyze different Network-on-Chip (NoC) designs with Static Random Access Memory (SRAM) Last Level Cache (LLC) and Dynamic Random Access Memory (DRAM) LLC. Different 2D/3D NoCs with SRAM/DRAM are modeled based on state-of-the-art chips. The impact of integrating DRAM cache into a NoC platform is discussed. We explore the advantages and disadvantages of DRAM cache for NoC in terms of access latency, cache size, area and power consumption. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average cache hit latencies in two DRAM based designs are increased by 12.53% (2D) and reduced by 27.97% (3D) respectively compared with the SRAM. It is also shown that the power consumption is a tradeoff consideration in improving the cache hit latency of DRAM LLC. Overall, the power consumption of 3D NoC design with DRAM LLC has reduced 25.78% compared with the SRAM design. Our analysis and experimental results provide a guideline to design efficient 3D NoCs with DRAM LLC.

Designing 2D and 3D Network-on-Chip Architectures

2014 ◽  
Author(s):  
Konstantinos Tatas ◽  
Kostas Siozios ◽  
Dimitrios Soudris ◽  
Axel Jantsch
Keyword(s):  
Network On Chip ◽  
3D Network ◽  
On Chip ◽  
2D And 3D

Power-and Thermal-aware Mapping for 3D Network-on-chip

2013 ◽  
Vol 12 (23) ◽  
pp. 7297-7304 ◽  
Author(s):  
Ge Fen ◽  
Feng Gui ◽  
Yu Shuang ◽  
Wu Ning
Keyword(s):  
Network On Chip ◽  
3D Network ◽  
On Chip

Low Temperature Direct Bond Technology for 3D Microelectronics Integration and Wafer Scale Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000015-000022
Author(s):  
Paul Enquist
Keyword(s):  
Low Temperature ◽  
Sensor Arrays ◽  
Cost Savings ◽  
Image Sensor ◽  
Network On Chip ◽  
Wafer Scale ◽  
Direct Bond ◽  
3D Network ◽  
On Chip ◽  
3D Volume

3D microelectronics integration and wafer scale packaging promise improvements in functional density and cost compared to conventional 2D microelectronics and packaging technologies. The realization of these improvements will require further adoption of 3D volume manufacturing process technologies. These process technologies will likely include through silicon via (TSV) and die or wafer bonding with and without 3D interconnect. Low temperature direct bond technologies have a number of inherent performance and cost advantages compared to other bonding technologies. This paper describes low temperature direct oxide bond technologies with and without a scalable 3D interconnect developed by Ziptronix and cost savings, performance and applications that will be enabled by adoption of these technologies. Enabled cost savings and performance include system or network-on-chip, system in package, and TSVs. Enabled applications include backside illuminated image sensors, micron-scale pitch vertically integrated image sensor arrays, 3D system-on-chip and 3D network-on-chip.

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