Enhancing Power Added Efficiency of Doherty Amplifier by Changing Power Ratio of Carrier Amplifier and Peak Amplifier

Author(s):  
Guanyu Mu ◽  
Hitoshi Hayashi
2014 ◽  
Vol 8 (9) ◽  
pp. 1280-1287 ◽  
Author(s):  
Matthew Fellows ◽  
Charles Baylis ◽  
Joshua Martin ◽  
Lawrence Cohen ◽  
Robert J. Marks

2021 ◽  
Author(s):  
Pouya Jahanian ◽  
Azadeh Norouzi Kangarshahi

Abstract In this paper, an attempt has been made to design a Doherty power amplifier (DPA) with high-gain and wide-band. For this purpose, two peak amplifiers are used to improve the performance of the main amplifier. Main and auxiliary amplifiers with the same structure to the class-AB type and by using micro-strip lines in place of input/output and load matching networks, transmission lines and inductors of drain and gate, that minimize the losses in the DPA. The current DPA is implemented with GaN_HEMT_CLF1G0530_100v transistor and Rogers4003 substrate, which for 1GHz frequency in 0.5-1.5GHz bandwidth will be able to be at P-1dB point (this point, input power as 30dBm and output power as 47.98dBm) increase Drain efficiency and Power added efficiency (PAE) to 81.95% and 80.73%, respectively. The DPA helps to expand the back-off region and extend the linearity region, so the Peak to average power ratio (PAPR) will be 5.21dB and the Adjacent channel power ratio (ACPR) as 58.7dBc. A gain of 17.06-17.92dB was also obtained, which is significant compared to the results of similar samples.


Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Saeedeh Lotfi ◽  
Saeed Roshani ◽  
Sobhan Roshani ◽  
Maryam Shirzadian Gilan

Abstract This paper presents a new Doherty power amplifier (DPA) with harmonics suppression. A Wilkinson power divider (WPD) with open-ended and short-ended stubs is designed to suppress unwanted signals. To design the power divider in the circuit of the DPA, even and odd mode analyses are utilized. The proposed design operates at range of 1.2–1.6 GHz. The linearity of the suggested DPA is increased about 6 dBm, in comparison with the main amplifier. The designed Doherty amplifier has a power added efficiency (PAE), drain efficiency (DE) and Gain about 60, 61% and 19 dB, respectively. The designed WPD suppresses 2nd up to 14th harmonics with more than 20 dB suppression level, which is useful for suppressing unwanted harmonics in DPA design. ATF-34143 transistors (pHEMT technology) are used for this DPA amplifier design. The main amplifier has class-F topology and class-F inverse topology is used for auxiliary amplifier.


Author(s):  
Khaled Bathich ◽  
Georg Boeck

This paper presents the analysis and design of a wideband asymmetrical Doherty amplifier. The frequency response of the output combining network of the Doherty amplifier with arbitrary back-off level configuration is analyzed. Other bandwidth-limiting factors were discussed and analyzed as well. A number of performance enhancement techniques were taken into consideration to obtain high and flat back-off efficiency over the amplifier design band of 1.7–2.25 GHz. The designed Doherty amplifier had, at 8.0–9.9 dB output back-off, a minimum efficiency of η = 50% [power-added efficiency of 45%], measured near 40 dBm of output power, and over 28% bandwidth. Using digital predistortion (DPD) linearization, an adjacent-channel leakage ratio (ACLR) of −43 dBc was obtained for a single-carrier W-CDMA signal, at 40.9 dBm and 46% of average output power and drain efficiency, respectively. The designed amplifier represents the first wideband Doherty amplifier reported over extended power back-off range.


Author(s):  
Andres Seidel ◽  
Jens Wagner ◽  
Frank Ellinger

Abstract This paper investigates the frequency response of load modulation networks for asymmetric Doherty power amplifiers (ADPA) with an output back-off power level larger than 6 dB and a power ratio of peak to main amplifier (N − 1) larger than 1. The influence of the main path impedance transformer (IT) on the Doherty impedances at main and peak path as well as on the ADPA's efficiency is analyzed. Scaling of the main IT's characteristic impedance via ξ indicates a maximum broadband matching for an input voltage Vin of ξ · Vin,max. By weighting the frequency- and ξ-dependent efficiency curves using a probability density function (PDF), an optimum is obtained for ξ = 1/N. To verify the theory, three ADPAs with different ξ-scaled ITs are designed, measured, and compared. For the design at 3.6 GHz, a gallium nitride (GaN) transistor is used. By means of the intrinsic node matching technique, matching at the current source plane is obtained. In laboratory measurements, the ADPA with ξ = 1/N achieves a power-added efficiency (PAE) of 63% at 42 dBm output power and a PDF-weighted average PAE of 38.8% within 400 MHz bandwidth for 8 dB peak-to-average power ratio. Comparison with similar state-of-the-art ADPAs in GaN technology shows highest PAE and operation power gain GP for center frequencies larger than 3.0 GHz.


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