A planner Doherty power amplifier with harmonic suppression with open and short ended stubs

Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Saeedeh Lotfi ◽  
Saeed Roshani ◽  
Sobhan Roshani ◽  
Maryam Shirzadian Gilan
Keyword(s):  
Power Amplifier ◽  
Power Divider ◽  
Harmonic Suppression ◽  
Power Added Efficiency ◽  
Main Amplifier ◽  
Inverse Topology ◽  
Doherty Power Amplifier ◽  
Amplifier Design ◽  
Doherty Amplifier ◽  
Class F

Abstract This paper presents a new Doherty power amplifier (DPA) with harmonics suppression. A Wilkinson power divider (WPD) with open-ended and short-ended stubs is designed to suppress unwanted signals. To design the power divider in the circuit of the DPA, even and odd mode analyses are utilized. The proposed design operates at range of 1.2–1.6 GHz. The linearity of the suggested DPA is increased about 6 dBm, in comparison with the main amplifier. The designed Doherty amplifier has a power added efficiency (PAE), drain efficiency (DE) and Gain about 60, 61% and 19 dB, respectively. The designed WPD suppresses 2nd up to 14th harmonics with more than 20 dB suppression level, which is useful for suppressing unwanted harmonics in DPA design. ATF-34143 transistors (pHEMT technology) are used for this DPA amplifier design. The main amplifier has class-F topology and class-F inverse topology is used for auxiliary amplifier.

scholarly journals A Broadband Asymmetrical GaN MMIC Doherty Power Amplifier with Compact Size for 5G Communications

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 311
Author(s):  
Peisen Cheng ◽  
Quan Wang ◽  
Wei Li ◽  
Yeting Jia ◽  
Zhichao Liu ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Integrated Circuit ◽  
Power Divider ◽  
Total Power ◽  
Design System ◽  
Power Added Efficiency ◽  
Matching Networks ◽  
Compact Size ◽  
Doherty Power Amplifier

This paper proposes a broadband asymmetrical monolithic microwave integrated circuit (MMIC) Doherty power amplifier (DPA) using 0.25-μm gallium-nitride process with a compact chip size of 2.37 × 1.86 mm2 for 5G communication. It adopts an unequal Wilkinson’s power divider with a ratio of 2.5:1, where 71.5% of the total power is transferred to the main amplifier for higher gain. Different input matching networks are used to offset phase difference while completing impedance conversion. This design also applies a novel topology to solve the problem of large impedance transformer ratio (ITR) in conventional DPA, and it optimizes the ITR from 4:1 to 2:1 for wider band. Moreover, most of the components of the DPA including power divider and matching networks use lumped inductors and capacitors instead of long transmission line (TL) for a smaller space area. The whole circuit is designed and simulated using Agilent’s advanced design system (ADS). The simulated small-signal gain of DPA is 8–11 dB and the saturation output power is more than 39.5 dBm with 800 MHz band from 4.5 GHz to 5.3 GHz. At 6-dB output power back-off, the DPA demonstrates 38–41.3% power added efficiency (PAE), whereas 44–54% PAE is achieved at saturation power.

scholarly journals A two-stage power amplifier design for ultra-wideband applications

2021 ◽  
Vol 11 (1) ◽  
pp. 772
Author(s):  
Idrees S. Al-Kofahi ◽  
Zaid Albataineh ◽  
Ahmad Dagamseh
Keyword(s):  
Power Amplifier ◽  
Ultra Wideband ◽  
Common Source ◽  
Two Stage ◽  
Output Node ◽  
Load Impedance ◽  
Power Added Efficiency ◽  
Main Amplifier ◽  
Amplifier Design ◽  
5 Ghz

In this paper, a two-stage 0.18 μm CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz based on common source inductive degeneration with an auxiliary amplifier is proposed. In this proposal, an auxiliary amplifier is used to place the 2nd harmonic in the core amplified in order to make up for the gain progression phenomena at the main amplifier output node. Simulation results show a power gain of 16 dB with a gain flatness of 0.4 dB and an input 1 dB compression of about -5 dBm from 3 to 5 GHz using a 1.8 V power supply consuming 25 mW. Power added efficiency (PAE) of around 47% at 4 GHz with 50 Ω load impedance was also observed.

A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Premmilaah Gunasegaran ◽  
Jagadheswaran Rajendran ◽  
Selvakumar Mariappan ◽  
Yusman Mohd Yusof ◽  
Zulfiqar Ali Abdul Aziz ◽  
...  
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Power Amplifier ◽  
Maximum Output Power ◽  
Maximum Output ◽  
Power Gain ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Main Amplifier

Purpose The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability. Findings With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation. Practical implications The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design. Originality/value The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

Design of a Miniaturized Class F Power Amplifier Using Capacitor Loaded Transmission Lines

Frequenz ◽  
2020 ◽  
Vol 74 (3-4) ◽  
pp. 145-152
Author(s):  
Ali Pirasteh ◽  
Saeed Roshani ◽  
Sobhan Roshani
Keyword(s):  
Power Amplifier ◽  
Mobile Communications ◽  
Transmission Lines ◽  
Low Voltage ◽  
Good Choice ◽  
Band Frequency ◽  
Power Added Efficiency ◽  
Harmonic Control ◽  
Measurement Results ◽  
Class F

AbstractIn this paper, a new method to decrease the dimensions of the microstrip structures and reducing the overall size of the class F amplifiers is presented. First, by using the PHEMT transistor with a conventional harmonic control circuit (HCC), a low-voltage class F amplifier in the L band frequency at the operating frequency of 1.75 GHz is introduced, which named primitive class F power amplifier. Then, this amplifier is optimized by using capacitor loaded transmission lines (CLTLs). The measurement results of the amplifier show that by using the CLTL structure, the overall size has been reduced 85% (0.23 λg × 0.17 λg). The maximum power-added efficiency (PAE) of the power amplifier is about 77.5 % and the power gain which has been reached to 18.33 dB. The desirable features of this power amplifier, along with its very small size, make this power amplifier a good choice to use for the global system for mobile communications.

scholarly journals Efficient technique for ultra broadband, linear power amplifier design

2012 ◽  
Vol 4 (6) ◽  
pp. 559-567 ◽  
Author(s):  
Ahmed Sayed ◽  
Sebastian Preis ◽  
Georg Boeck
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Impedance Matching ◽  
Network Synthesis ◽  
Circuit Performance ◽  
Power Added Efficiency ◽  
Starting Point ◽  
Saturated Output Power ◽  
Linear Power Amplifier ◽  
Amplifier Design

In this paper, a 10 W ultra-broadband GaN power amplifier (PA) is designed, fabricated, and tested. The suggested design technique provides a more accurate starting point for matching network synthesis and better prediction of achievable circuit performance. A negative-image model was used to fit the extracted optimum impedances based on source-/load-pull technique and multi-section impedance matching networks were designed. The implemented amplifier presents an excellent broadband performance, resulting in a gain of 8.5 ± 0.5 dB, saturated output power of ≥10 W, and power added efficiency (PAE) of ≥23% over the whole bandwidth. The linearity performance has also been characterized. An output third-order intercept point (OIP3) of ≥45 dBm was extracted based on a two-tone measurement technique in the operating bandwidth with different frequency spacing values. The memory effect based on AM/AM and AM/PM conversions was also characterized using a modulated WiMAX signal of 10 MHz bandwidth at 5.8 GHz. Furthermore, a broadband Wilkinson combiner was designed for the same bandwidth with very low loss to extend the overall output power. Excellent agreement between simulated and measured PA performances was also achieved.

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