A dual-code-rate memoryless Viterbi decoder for wireless communication systems

2013 ◽  
Author(s):  
Chu Yu ◽  
Yu-Shan Su ◽  
Bor-Shing Lin ◽  
Po-Hsun Cheng ◽  
Sao-Jie Chen
Keyword(s):  
Wireless Communication ◽  
Communication Systems ◽  
Code Rate ◽  
Dual Code ◽  
Wireless Communication Systems ◽  
Viterbi Decoder

ESTIMATION OF THE PROBABILITY TO DETECT SIGNALS OF WIRELESS COMMUNICATION SYSTEMS WITH WIRETAP CHANNELS WITH ANTENNAS APERTURES OF DIFFERENT SIZES AND RELATIVE POSITION

2011 ◽  
Vol 70 (7) ◽  
pp. 601-606 ◽  
Author(s):  
A. A. Strelnitskiy ◽  
A. E. Strelnitskyi ◽  
A. I. Tsopa ◽  
Viktoriya M. Shokalo ◽  
E.V. Yagudina
Keyword(s):  
Wireless Communication ◽  
Relative Position ◽  
Communication Systems ◽  
Wireless Communication Systems ◽  
Wiretap Channels

TRIPLET SIGNAL GENERATION FOR BISPECTRUM-BASED DIGITAL WIRELESS COMMUNICATION SYSTEMS

2015 ◽  
Vol 74 (8) ◽  
pp. 695-707 ◽  
Author(s):  
V. V. Naumenko ◽  
V.F. Solodovnik ◽  
A. V. Totskiy ◽  
J. T. Astola
Keyword(s):  
Wireless Communication ◽  
Communication Systems ◽  
Signal Generation ◽  
Wireless Communication Systems ◽  
Triplet Signal

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

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