Low power multiplier architectures using vedic mathematics in 45nm technology for high speed computing

2015 ◽  
Author(s):  
Suryasnata Tripathy ◽  
L B Omprakash ◽  
Sushanta K. Mandal ◽  
B S Patro
Keyword(s):  
Low Power ◽  
High Speed ◽  
Vedic Mathematics ◽  
Low Power Multiplier

scholarly journals Low Power 32 x 32 – bit Reversible Vedic Multiplier

2019 ◽  
Vol 8 (10) ◽  
pp. 852-856
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Reversible Logic ◽  
Low Power Consumption ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
X 32

Recently, low-power consuming devices are gaining demand due to excessive use and requirement of hand-held & portable electronic gadgets. The quest for designing better options to lower the power consumption of a device is in high-swing. The paper proposes two 32 x 32 – bit multipliers. The first design is based only on the Urdhava Tiryakbhyam Sutra of Vedic Mathematics. The use of this sutra has created a multiplier with higher throughput and lesser power utilization than conventional 32 x 32 – bit multipliers. The second design incorporates the reversible logic into the first design, which further reduces the power consumption of the system. Thus bringing together Vedic sutra for multiplication and reversible gates has led to the development of a Reversible Vedic Multiplier which has both the advantages of high-speed and low-power consumption.

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

2011 ◽  
Vol 42 (12) ◽  
pp. 1343-1352 ◽  
Author(s):  
P. Saha ◽  
A. Banerjee ◽  
A. Dandapat ◽  
P. Bhattacharyya
Keyword(s):  
Low Power ◽  
High Speed ◽  
Power Circuit ◽  
Vedic Mathematics ◽  
Asic Design

scholarly journals Design and Performance Analysis of Low Power High Speed Adder and Multiplier Using MTCMOS in 90nm, 70nm, 25nm and 18nm Regime

2021 ◽  
Author(s):  
Kalpana.K ◽  
Paulchamy. B ◽  
Priyadharsini. R ◽  
Arun Kumar Sivaraman ◽  
Rajiv Vincent ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Arithmetic Operation ◽  
Low Power Consumption ◽  
Vlsi Technology ◽  
And Performance ◽  
System Designs ◽  
Speed Propagation ◽  
Low Power Multiplier ◽  
Logic Unit

Nowadays, VLSI technology mainly focused on High-Speed Propagation and Low Power Consumption. Addition is an important arithmetic operation which plays a major role in digital application. Adder is act as an important role in the applications of signal processing, in memory access address generation and Arithmetic Logic Unit. When the number of transistors increases in system designs, makes to increase power and complexity of the circuit. One of the dominant factors is power reduction in low power VLSI technology and to overcome the power dissipation in the existing adder circuit, MTCMOS technique is used in the proposed adder. The design is simulated in 90nm, 70nm, 25nm and 18nm technology and then comparison is made between existing and proposed system in the context of energy, area and delay. In this comparison, the efficiency metrics power and delay are found to be reduced 20% from the existing adder and the proposed adder is used for the design of low power multiplier.

scholarly journals Design of High Speed and Low Power Multiplier using Dual-Mode Square Adder

2019 ◽  
Vol 3 (1) ◽  
pp. 1
Author(s):  
Naresh K. Darimireddy ◽  
B. Jaya Lakshmi ◽  
R. Ramana Reddy
Keyword(s):  
Low Power ◽  
High Speed ◽  
Dual Mode ◽  
Low Power Multiplier
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