scholarly journals Design and Performance Analysis of Low Power High Speed Adder and Multiplier Using MTCMOS in 90nm, 70nm, 25nm and 18nm Regime

2021 ◽  
Author(s):  
Kalpana.K ◽  
Paulchamy. B ◽  
Priyadharsini. R ◽  
Arun Kumar Sivaraman ◽  
Rajiv Vincent ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Arithmetic Operation ◽  
Low Power Consumption ◽  
Vlsi Technology ◽  
And Performance ◽  
System Designs ◽  
Speed Propagation ◽  
Low Power Multiplier ◽  
Logic Unit

Nowadays, VLSI technology mainly focused on High-Speed Propagation and Low Power Consumption. Addition is an important arithmetic operation which plays a major role in digital application. Adder is act as an important role in the applications of signal processing, in memory access address generation and Arithmetic Logic Unit. When the number of transistors increases in system designs, makes to increase power and complexity of the circuit. One of the dominant factors is power reduction in low power VLSI technology and to overcome the power dissipation in the existing adder circuit, MTCMOS technique is used in the proposed adder. The design is simulated in 90nm, 70nm, 25nm and 18nm technology and then comparison is made between existing and proposed system in the context of energy, area and delay. In this comparison, the efficiency metrics power and delay are found to be reduced 20% from the existing adder and the proposed adder is used for the design of low power multiplier.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals A high-speed hybrid Full Adder with low power consumption

2012 ◽  
Vol 9 (24) ◽  
pp. 1900-1905
Author(s):  
Kamran Delfan Hemmati ◽  
Mojtaba Behzad Fallahpour ◽  
Abbas Golmakani ◽  
Kamyar Delfan Hemmati
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Low Power Consumption

scholarly journals Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

2008 ◽  
Vol 29 (10) ◽  
pp. 1094-1097 ◽  
Author(s):  
G. Dewey ◽  
M.K. Hudait ◽  
Kangho Lee ◽  
R. Pillarisetty ◽  
W. Rachmady ◽  
...  
Keyword(s):  
Quantum Well ◽  
Low Power ◽  
High Speed ◽  
Carrier Transport ◽  
High Mobility ◽  
Performance Impact ◽  
And Performance ◽  
Low Power Logic

scholarly journals Low power and high speed GDI based convolution using Vedic multiplier

2018 ◽  
Vol 7 (2.7) ◽  
pp. 733
Author(s):  
C Priyanka ◽  
N Manoj Kumar ◽  
L Sai Priya ◽  
B Vaishnavi ◽  
M Rama Krishna
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
Digital Signal ◽  
Building Blocks ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Basic Building Block ◽  
Extensive Area ◽  
Vedic Multiplier

Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system.  Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of the system.  Several methods are designed to progress the speed of the Multiplier and adder, among all GDI (Gate Diffusion Input) is under emphasis because of faster working and low power consumption. In this paper GDI based convolution is implemented using Vedic multiplier and adder in T-SPICE Software which increases the speed and consumes less power compared to CMOS technology. 

scholarly journals Integration of highly anisotropic multiferroic BaTiO3–Fe nanocomposite thin films on Si towards device applications

2020 ◽  
Vol 2 (9) ◽  
pp. 4172-4178
Author(s):  
Matias Kalaswad ◽  
Bruce Zhang ◽  
Xuejing Wang ◽  
Han Wang ◽  
Xingyao Gao ◽  
...  
Keyword(s):  
Thin Films ◽  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Low Cost ◽  
Low Power Consumption ◽  
Silicon Substrates ◽  
Critical Step ◽  
Nanocomposite Thin Films ◽  
Device Applications

Integration of highly anisotropic multiferroic thin films on silicon substrates is a critical step towards low-cost devices, especially high-speed and low-power consumption memories.

A GaAs monolithic amplifier with extremely low power consumption

1991 ◽  
Vol 69 (3-4) ◽  
pp. 177-179
Author(s):  
Langis Roy ◽  
Malcolm G. Stubbs ◽  
James S. Wight
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Gain ◽  
Low Power Consumption ◽  
Monolithic Microwave Integrated Circuit ◽  
Dc Power ◽  
Broadband Amplifier ◽  
Effect Transistor ◽  
And Performance

The design and performance of a high-gain, monolithic, broadband amplifier with extremely low power consumption are described. The amplifier, fabricated using a 0.5 μm GaAs depletion-mode MESFET (metal semiconductor field effect transistor) process, utilizes very small gate width devices to achieve a measured gain of 19 dB and a 0.1 to 2.1 GHz bandwidth with only 63 mW dc power dissipation. This is the lowest power consumption broadband MMIC (monolithic microwave integrated circuit) reported to date and is intended for mobile radio applications.

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