A parallel architecture for efficient reverse converter using Chinese remainder theorem

2015 ◽  
Author(s):  
Vivek Pralhadrao Sahare ◽  
S. V. Rathkanthiwar
Keyword(s):  
Chinese Remainder Theorem ◽  
Parallel Architecture ◽  
Reverse Converter

Efficiency Reverse Converter for 4-Moduli Set {22n, 22n+1-1, 2n+1, 2n-1} Based on New CRT-II

2013 ◽  
Vol 336-338 ◽  
pp. 1852-1856
Author(s):  
Siang Min Siao ◽  
Yuan Ching Kuo ◽  
Ming Hwa Sheu ◽  
Xin Kun Lin ◽  
Tzu Hsiung Chen
Keyword(s):  
Efficient Algorithm ◽  
Chinese Remainder Theorem ◽  
Reverse Converter

In this paper, the new 4-moduli set {22n, 22n+1-1, 2n+1, 2n-1} with 6n-bit DR, which is appropriate for RNS applications. An efficient algorithm for residue-to-binary conver­sion is derived based on New Chinese remainder theorem II (New CRT-II). Next, the converter hardware is also designed to achieve average 36.6% performance saving in terms of the Area× Delay when comparing with the latest converter with 4-moduli set under the same DR require­ment.

scholarly journals New Adder-Based RNS-to-Binary Converters for the Moduli Set

2011 ◽  
Vol 2011 ◽  
pp. 1-7
Author(s):  
Kazeem Alagbe Gbolagade
Keyword(s):  
State Of The Art ◽  
Chinese Remainder Theorem ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Hardware Complexity ◽  
Reverse Converter ◽  
Efficient Scheme ◽  
Cost Efficient ◽  
Two Hybrid

We investigate Residue Number System (RNS) to binary conversion, which is an important issue concerning the utilization of RNS numbers in Digital Signal Processing (DSP) applications. We propose two new reverse converters for the moduli set . First, we simplify the Chinese Remainder Theorem (CRT) to obtain a reverse converter that uses mod- operations instead of mod- operations required by other state-of-the-art equivalent converters. Next, we further reduce the hardware complexity by making the resulting reverse converter architecture adder based. Two hybrid Cost-Efficient (CE) and Speed-Efficient (SE) reverse converters are proposed. These two hybrid converters are obtained by combining the best state-of-the-art converter with the newly introduced area-delay efficient scheme. The proposed hybrid CE converter outperforms the best state-of-the-art CE converter in terms of delay with similar area cost. Additionally, the proposed hybrid SE converter requires less area cost with smaller delay when compared to the best state-of-the-art equivalent SE converter.

The Recent Revolution in High Performance Computing

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 5-6
Author(s):  
Horst D. Simon
Keyword(s):  
High Performance Computing ◽  
High Performance ◽  
New Technologies ◽  
New Technology ◽  
Parallel Architecture ◽  
Time Frame ◽  
Good News ◽  
Computing Industry ◽  
Time And Energy ◽  
Performance Computing

Recent events in the high-performance computing industry have concerned scientists and the general public regarding a crisis or a lack of leadership in the field. That concern is understandable considering the industry's history from 1993 to 1996. Cray Research, the historic leader in supercomputing technology, was unable to survive financially as an independent company and was acquired by Silicon Graphics. Two ambitious new companies that introduced new technologies in the late 1980s and early 1990s—Thinking Machines and Kendall Square Research—were commercial failures and went out of business. And Intel, which introduced its Paragon supercomputer in 1994, discontinued production only two years later.During the same time frame, scientists who had finished the laborious task of writing scientific codes to run on vector parallel supercomputers learned that those codes would have to be rewritten if they were to run on the next-generation, highly parallel architecture. Scientists who are not yet involved in high-performance computing are understandably hesitant about committing their time and energy to such an apparently unstable enterprise.However, beneath the commercial chaos of the last several years, a technological revolution has been occurring. The good news is that the revolution is over, leading to five to ten years of predictable stability, steady improvements in system performance, and increased productivity for scientific applications. It is time for scientists who were sitting on the fence to jump in and reap the benefits of the new technology.

PROTEUS: A High-Performance Parallel-Architecture Simulator

1991 ◽  
Author(s):  
Eric A. Brewer ◽  
Chrysanthos N. Dellarocas ◽  
Adrian Colbrook ◽  
William E. Weihl
Keyword(s):  
High Performance ◽  
Parallel Architecture

Analysis and Design of High Speed Residue to Binary Reverse Converter for the Moduli Set {2n+ 1, 2n,2n-1}

2020 ◽  
Author(s):  
K. Vijaya Vardhan ◽  
Gonuguntla Sailakshmi ◽  
Sarada Musala ◽  
Avireni Srinivasulu
Keyword(s):  
High Speed ◽  
Analysis And Design ◽  
Reverse Converter

scholarly journals Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1106
Author(s):  
Vladimir L. Petrović ◽  
Dragomir M. El Mezeni ◽  
Andreja Radošević
Keyword(s):  
Channel Coding ◽  
Parallel Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Case Scenario ◽  
New Radio ◽  
Physical Channel ◽  
Computationally Intensive ◽  
Hardware Processing ◽  
Usage Efficiency

Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.

scholarly journals Secure Video Surveillance Framework in Smart City

Sensors ◽  
2021 ◽  
Vol 21 (13) ◽  
pp. 4419
Author(s):  
Hao Li ◽  
Tianhao Xiezhang ◽  
Cheng Yang ◽  
Lianbing Deng ◽  
Peng Yi
Keyword(s):  
Video Surveillance ◽  
Smart City ◽  
Key Management ◽  
Surveillance System ◽  
Chinese Remainder Theorem ◽  
Smart Cities ◽  
Group Key Management ◽  
Video Surveillance System ◽  
Surveillance Systems ◽  
Key Update

In the construction process of smart cities, more and more video surveillance systems have been deployed for traffic, office buildings, shopping malls, and families. Thus, the security of video surveillance systems has attracted more attention. At present, many researchers focus on how to select the region of interest (RoI) accurately and then realize privacy protection in videos by selective encryption. However, relatively few researchers focus on building a security framework by analyzing the security of a video surveillance system from the system and data life cycle. By analyzing the surveillance video protection and the attack surface of a video surveillance system in a smart city, we constructed a secure surveillance framework in this manuscript. In the secure framework, a secure video surveillance model is proposed, and a secure authentication protocol that can resist man-in-the-middle attacks (MITM) and replay attacks is implemented. For the management of the video encryption key, we introduced the Chinese remainder theorem (CRT) on the basis of group key management to provide an efficient and secure key update. In addition, we built a decryption suite based on transparent encryption to ensure the security of the decryption environment. The security analysis proved that our system can guarantee the forward and backward security of the key update. In the experiment environment, the average decryption speed of our system can reach 91.47 Mb/s, which can meet the real-time requirement of practical applications.

Parallel architecture and compilation techniques

2001 ◽  
Vol 29 (5) ◽  
pp. 9-12
Author(s):  
S. Bartolini ◽  
R. Giorgi ◽  
J. Protic ◽  
C. A. Prete ◽  
M. Valero
Keyword(s):  
Parallel Architecture ◽  
Compilation Techniques
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